更新 try_smg/counter.v

try_smg/counter.v

@@ -1,15 +1,14 @@
-module counter
+module counter
-(
+(
-    input clk, enable, rst_n,
+    input clk, enable, rst_n,
-    output reg [8-1:0] count
+    output reg [8-1:0] count
-);
+);
-
+
-always @ (posedge clk or negedge rst_n)
+always @ (posedge clk or negedge rst_n)
-begin
+begin
-    if (!rst_n)
+    if (!rst_n)
-        count <= 0;
+        count <= 0;
-    else if (enable == 1'b1)
+    else if (enable == 1'b1)
-        count <= count + 1;
+        count <= count + 1;
-end
+end
-
 endmodule