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更新 try_smg/counter.v

This commit is contained in:
yangshenbo 2025-12-03 16:46:03 +08:00
parent 223768a057
commit f89c74205a
1 changed files with 13 additions and 14 deletions
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27
try_smg/counter.v
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@ -1,15 +1,14 @@
module counter
(
input clk, enable, rst_n,
output reg [8-1:0] count
);
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
count <= 0;
else if (enable == 1'b1)
count <= count + 1;
end
module counter
(
input clk, enable, rst_n,
output reg [8-1:0] count
);
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
count <= 0;
else if (enable == 1'b1)
count <= count + 1;
end
endmodule