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删除了try_smg这个尝试文件

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yangshenbo 2026-01-09 19:21:17 +08:00
parent c24fb99bbf
commit 7f8e4a0715
4 changed files with 0 additions and 108 deletions
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15
try_smg/counter.v
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module counter
(
input clk, enable, rst_n,
output reg [8-1:0] count
);
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
count <= 0;
else if (enable == 1'b1)
count <= count + 1;//aabbcc
end
endmodule

46
try_smg/exp6_changed.v
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module exp6_changed(
input clk,pbl,enable,
output [7-1:0] led_high,led_low
);
wire clk_3Hz;
wire[7:0] cnt;
reg clk_3Hz_ff0;
wire positive_edge_clk3Hz;
freq_div #(
.n(3)
) u_freq_div(
.clk(clk),
.rst_n(pbl),
.freqdiv_out(clk_3Hz)
);
always @ (posedge clk or negedge pbl)
begin
if (!pbl)
clk_3Hz_ff0 <= 0;
else
clk_3Hz_ff0 <= clk_3Hz;
end
assign positive_edge_clk3Hz = clk_3Hz==1 && clk_3Hz_ff0==0;
counter u_counter(
.clk(clk),
.enable(enable && positive_edge_clk3Hz),
.rst_n(pbl),
.count(cnt)
);
seg7_led u_seg7_led_high(
.data_in(cnt[7:4]),
.led_out(led_high)
);
seg7_led u_seg7_led_low(
.data_in(cnt[3:0]),
.led_out(led_low)
);
endmodule

21
try_smg/freq_div.v
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module freq_div
#(
parameter n
)
(
input clk,rst_n,
output freqdiv_out
);
reg [n-1:0] count;
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
count <= 0;
else
count <= count + 1;
end
assign freqdiv_out = count[n-1];
//feature
endmodule

26
try_smg/seg7_led.v
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module seg7_led(
input [4-1:0] data_in,
output reg [7-1:0] led_out
);
always @(*) begin
case(data_in)
4'h0:led_out = 7'b1000000;
4'h1:led_out = 7'b1111001;
4'h2:led_out = 7'b0100100;
4'h3:led_out = 7'b0110000;
4'h4:led_out = 7'b0011001;
4'h5:led_out = 7'b0010010;
4'h6:led_out = 7'b0000010;
4'h7:led_out = 7'b1111000;
4'h8:led_out = 7'b0000000;
4'h9:led_out = 7'b0010000;
4'ha:led_out = 7'b0001000;
4'hb:led_out = 7'b0000011;
4'hc:led_out = 7'b1000110;
4'hd:led_out = 7'b0100001;
4'he:led_out = 7'b0000110;
4'hf:led_out = 7'b0001110;
default:led_out = 7'b1111111;
endcase
end
endmodule