diff --git a/try_smg/counter.v b/try_smg/counter.v
deleted file mode 100644
index ff8f973..0000000
--- a/try_smg/counter.v
+++ /dev/null
@@ -1,15 +0,0 @@
-module counter
-(
-    input clk, enable, rst_n,
-    output reg [8-1:0] count
-);
-
-always @ (posedge clk or negedge rst_n)
-begin
-    if (!rst_n)
-        count <= 0;
-    else if (enable == 1'b1)
-        count <= count + 1;//aabbcc
-end
-
-endmodule
\ No newline at end of file
diff --git a/try_smg/exp6_changed.v b/try_smg/exp6_changed.v
deleted file mode 100644
index 27d9b4e..0000000
--- a/try_smg/exp6_changed.v
+++ /dev/null
@@ -1,46 +0,0 @@
-module exp6_changed(
-    input clk,pbl,enable,
-    output [7-1:0] led_high,led_low
-);
-
-wire clk_3Hz;
-wire[7:0] cnt;
-reg clk_3Hz_ff0;
-wire positive_edge_clk3Hz;
-
-freq_div #(
-    .n(3)
-) u_freq_div(
-    .clk(clk),
-    .rst_n(pbl),
-    .freqdiv_out(clk_3Hz)
-);
-
-always @ (posedge clk or negedge pbl)
-begin
-    if (!pbl)
-        clk_3Hz_ff0 <= 0;
-    else
-        clk_3Hz_ff0 <= clk_3Hz;
-end
-
-assign positive_edge_clk3Hz = clk_3Hz==1 && clk_3Hz_ff0==0;
-
-counter u_counter(
-    .clk(clk),
-    .enable(enable && positive_edge_clk3Hz),
-    .rst_n(pbl),
-    .count(cnt)
-);
-
-seg7_led u_seg7_led_high(
-    .data_in(cnt[7:4]),
-    .led_out(led_high)
-);
-
-seg7_led u_seg7_led_low(
-    .data_in(cnt[3:0]),
-    .led_out(led_low)
-);
-
-endmodule
\ No newline at end of file
diff --git a/try_smg/freq_div.v b/try_smg/freq_div.v
deleted file mode 100644
index 7762cbd..0000000
--- a/try_smg/freq_div.v
+++ /dev/null
@@ -1,21 +0,0 @@
-module freq_div
-#(
-    parameter n
-)
-(
-    input clk,rst_n,
-    output freqdiv_out
-);
-
-reg [n-1:0] count;
-
-always @(posedge clk or negedge rst_n) begin
-    if (!rst_n)
-        count <= 0;
-    else
-        count <= count + 1;
-end
-
-assign freqdiv_out = count[n-1];
-//feature
-endmodule
\ No newline at end of file
diff --git a/try_smg/seg7_led.v b/try_smg/seg7_led.v
deleted file mode 100644
index 969747a..0000000
--- a/try_smg/seg7_led.v
+++ /dev/null
@@ -1,26 +0,0 @@
-module seg7_led(
-	input [4-1:0] data_in,
-	output reg [7-1:0] led_out
-);
-always @(*) begin
-	case(data_in)
-		4'h0:led_out = 7'b1000000;
-		4'h1:led_out = 7'b1111001;
-		4'h2:led_out = 7'b0100100;
-		4'h3:led_out = 7'b0110000;
-		4'h4:led_out = 7'b0011001;
-		4'h5:led_out = 7'b0010010;
-		4'h6:led_out = 7'b0000010;
-		4'h7:led_out = 7'b1111000;
-		4'h8:led_out = 7'b0000000;
-		4'h9:led_out = 7'b0010000;
-		4'ha:led_out = 7'b0001000;
-		4'hb:led_out = 7'b0000011;
-		4'hc:led_out = 7'b1000110;
-		4'hd:led_out = 7'b0100001;
-		4'he:led_out = 7'b0000110;
-		4'hf:led_out = 7'b0001110;
-		default:led_out = 7'b1111111;
-	endcase
-end
-endmodule