From 7b85b7cadd71a90ad2938f696ba5ce9f36b356fb Mon Sep 17 00:00:00 2001 From: yangshenbo Date: Fri, 9 Jan 2026 21:46:56 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BB=BF=E7=9C=9F=E6=97=A0=E8=AF=AF=EF=BC=8C?= =?UTF-8?q?=E6=88=90=E5=8A=9F=E5=B0=86=E4=B8=80=E4=B8=AAudp=E7=AB=AF?= =?UTF-8?q?=E5=8F=A3=E5=8F=98=E6=88=90=E4=B8=A4=E4=B8=AA=E7=AB=AF=E5=8F=A3?= =?UTF-8?q?=E2=80=94=E2=80=94udp=20process=20data=E4=B8=BA=E6=9D=BF?= =?UTF-8?q?=E7=BA=A7=E5=86=99=E6=B3=95?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- UDP_data_process.v | 60 ++++++---- .../a83dc5096e9434783ed57f826a2f50e2.png | Bin 0 -> 10973 bytes .../局部截取_20260109_211301.png | Bin 0 -> 9212 bytes .../局部截取_20260109_211614.png | Bin 0 -> 15929 bytes .../局部截取_20260109_212429.png | Bin 0 -> 7127 bytes .../局部截取_20260109_214254.png | Bin 0 -> 13237 bytes readme/变成两个udp,一个负责收一个负责发.md | 81 +++++++++++++ status_to_udp.v | 113 ++++++++++++------ 8 files changed, 193 insertions(+), 61 deletions(-) create mode 100644 readme/变成两个udp,一个负责收一个负责发.assets/a83dc5096e9434783ed57f826a2f50e2.png create mode 100644 readme/变成两个udp,一个负责收一个负责发.assets/局部截取_20260109_211301.png create mode 100644 readme/变成两个udp,一个负责收一个负责发.assets/局部截取_20260109_211614.png create mode 100644 readme/变成两个udp,一个负责收一个负责发.assets/局部截取_20260109_212429.png create mode 100644 readme/变成两个udp,一个负责收一个负责发.assets/局部截取_20260109_214254.png create mode 100644 readme/变成两个udp,一个负责收一个负责发.md diff --git a/UDP_data_process.v b/UDP_data_process.v index 3a080dc..bf3385b 100644 --- a/UDP_data_process.v +++ b/UDP_data_process.v @@ -29,17 +29,25 @@ module UDP_data_process ( input eth_linked, output reg pulse_second, -// input data_fifo_rden, // UDP接收FIFO接口 - output reg udp_app_recv_fifo_rden, - input [7:0] udp_app_recv_fifo_rddata, - input [11:0] udp_app_recv_fifo_rdcnt, - input udp_app_recv_fifo_empty, - // UDP发送FIFO接口 - input udp_app_send_fifo_rden, - output [7:0] udp_app_send_fifo_rddata, - output [11:0] udp_app_send_fifo_rdcnt, - output udp_app_send_fifo_empty, + output reg udp_app_recv_fifo_rden_0, + input [7:0] udp_app_recv_fifo_rddata_0, + input [11:0] udp_app_recv_fifo_rdcnt_0, + input udp_app_recv_fifo_empty_0, + // UDP0发送FIFO接口 + input udp_app_send_fifo_rden_0, + output [7:0] udp_app_send_fifo_rddata_0, + output [11:0] udp_app_send_fifo_rdcnt_0, + output udp_app_send_fifo_empty_0, + + // UDP1接收FIFO接口 + //we don't need + + // UDP1发送FIFO接口 + input udp_app_send_fifo_rden_1, + output [7:0] udp_app_send_fifo_rddata_1, + output [11:0] udp_app_send_fifo_rdcnt_1, + output udp_app_send_fifo_empty_1, // TOE寄存器接口 output reg TOE_reg_wren, output reg TOE_reg_rden, @@ -63,7 +71,7 @@ module UDP_data_process ( input [31:0] DAQ_Status_Info_data ); -// wire udp_app_recv_fifo_rden_r; + wire udp_app_recv_fifo_ready; wire udp_recv_data_tvalid; wire [31:0]udp_recv_data; @@ -168,24 +176,23 @@ ila_00 ila_udp_data ( // --------------------------- always@(posedge clk) if(reset) - udp_app_recv_fifo_rden <= 1'b0; - else if(udp_app_recv_fifo_rdcnt == 12'b1) //上板后不得注释！！记得取消注释 //实际应该是读计数为1时候就要拉低了，不然板子会多读一个。 仿真又坑了我。跑一次比特流要15分钟呢！ //仿真需要 udp_app_recv_fifo_rdcnt == 12'b0 时才拉低 - udp_app_recv_fifo_rden <= 1'b0; - else if((~udp_app_recv_fifo_empty) && udp_app_recv_fifo_ready && (~deal_busy) && eth_linked) //如果连接成功才会去读,连接失败不能去读fifo。 - udp_app_recv_fifo_rden <= 1'b1; + udp_app_recv_fifo_rden_0 <= 1'b0; //仿真和上板的区别有2个地方，一个是这边，另外一个是秒脉冲的计数器（2处） + else if(udp_app_recv_fifo_rdcnt_0 == 12'b1) //上板后不得注释！！记得取消注释 //实际应该是读计数为1时候就要拉低了，不然板子会多读一个。 + udp_app_recv_fifo_rden_0 <= 1'b0; + else if((~udp_app_recv_fifo_empty_0) && udp_app_recv_fifo_ready && (~deal_busy) && eth_linked) //如果连接成功才会去读,连接失败不能去读fifo。 + udp_app_recv_fifo_rden_0 <= 1'b1; else - udp_app_recv_fifo_rden <= 1'b0; + udp_app_recv_fifo_rden_0 <= 1'b0; -//assign udp_app_recv_fifo_rden_r = udp_app_recv_fifo_rden && (~udp_app_recv_fifo_empty); // udp recv data does not delay, so the en needn't delay axis_dwidth_converter_0 axis_dwidth_converter_udprx( .aclk (clk), // input .aresetn (~reset), // input - .s_axis_tvalid(udp_app_recv_fifo_rden), // input + .s_axis_tvalid(udp_app_recv_fifo_rden_0), // input .s_axis_tready(udp_app_recv_fifo_ready), // output - .s_axis_tdata (udp_app_recv_fifo_rddata), // input [7:0] + .s_axis_tdata (udp_app_recv_fifo_rddata_0), // input [7:0] .m_axis_tvalid(udp_recv_data_tvalid), // output .m_axis_tready(1'b1), // input .m_axis_tdata (udp_recv_data) // output [63:0] @@ -448,10 +455,15 @@ status_to_udp status_to_udp_0 ( .DAQ_Status_Info_last(DAQ_Status_Info_last), .DAQ_Status_Info_data(DAQ_Status_Info_data), - .udp_app_send_fifo_rden(udp_app_send_fifo_rden), - .udp_app_send_fifo_rddata(udp_app_send_fifo_rddata), - .udp_app_send_fifo_rdcnt(udp_app_send_fifo_rdcnt), - .udp_app_send_fifo_empty(udp_app_send_fifo_empty) + .udp_app_send_fifo_rden_0(udp_app_send_fifo_rden_0), + .udp_app_send_fifo_rddata_0(udp_app_send_fifo_rddata_0), + .udp_app_send_fifo_rdcnt_0(udp_app_send_fifo_rdcnt_0), + .udp_app_send_fifo_empty_0(udp_app_send_fifo_empty_0), + + .udp_app_send_fifo_rden_1(udp_app_send_fifo_rden_1), + .udp_app_send_fifo_rddata_1(udp_app_send_fifo_rddata_1), + .udp_app_send_fifo_rdcnt_1(udp_app_send_fifo_rdcnt_1), + .udp_app_send_fifo_empty_1(udp_app_send_fifo_empty_1) ); diff --git a/readme/变成两个udp,一个负责收一个负责发.assets/a83dc5096e9434783ed57f826a2f50e2.png b/readme/变成两个udp,一个负责收一个负责发.assets/a83dc5096e9434783ed57f826a2f50e2.png new file mode 100644 index 0000000000000000000000000000000000000000..0c13a4bd0c231d96db377323c57ec0e0eaa4b218 GIT binary patch literal 10973 zcmb7~byQs6vgaFu1`DpiAy{w;5G1%uaQ8-nH5%L@xCe&-!J%LVf_DS_?`f-Mx9I-~zb5?6}Q`1^dpih3iGnQQO8=U#9 z(~UxTvvlYQ?S3B{4}X(uUP}iJUI{~3$D%M?WgW8Kq*!DTQdqGRX7-g#Y;nmg1Tt8+ zfV)hT}Pqxt!UlKU>V;W{Ly4Q!aTy}Y2>!0D+OrU_`^QwVBidv&FpMYkG3_25lx zT(~2H;hxZD0xzbB$88d4v74Gg8 zTB6MR^e-BFcP#;2LL6Hap~KntK243VN*5B6;`F` z^^HRBObS5p%s2!swytM?n_a(e#D_ca@6bZaf2w~pG5o<_cT(^cWL`x-{3R|>F5wo<~{a!13hozJ1eL7YeYNfk9Hpy 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+UDP_data_process.v主要负责接收UDP传过来的信息，然后执行对应操作。比如说接收到一个TOE写的网络包，然后会进行解析与执行。接收到开启秒脉冲的包，就会控制pluse_second。 + +转发功能全打包到status_to_udp.v中，实现功能解耦，代码也更好看。从TOE和另外3个信息模块拿到数据，打包成UDP帧结构，然后发送出去。 + +## 现在 + +![a83dc5096e9434783ed57f826a2f50e2](./变成两个udp,一个负责收一个负责发.assets/a83dc5096e9434783ed57f826a2f50e2.png) + +本来是一个udp接口收发数据，现在实际是两个。udp1只负责发送状态数据，**不需要接收**，udp0负责配置数据和指令等，**需要接收TOE命令**。所以在你的模块顶层会有两组这个udp数据接口。 + +# 改动 + +## status to udp + +仲裁存储状态机不用改。TOE valid的来进的是TOE_rec_fifo 。而状态信息进的是info_cache_fifo。 + +发送状态机需要改。关键是fifo_wr_en fifo_wr_data得改。 + +改了fifo发现，端口添加很容易，关键是添加了fifo_wr_en_TOE，fifo_wr_data_TOE！ + +## UDP_data_process + +除了端口改了。 + +由于该模块主要是执行功能，所以主要改接口就ok了 + +![局部截取_20260109_212429](./变成两个udp,一个负责收一个负责发.assets/局部截取_20260109_212429.png) + + + +# 仿真 + +## Status to udp 转发模块验证 + +### 保证状态信息info转发正确 + +//秒脉冲开启//////////////////////////////////// + + send_fifo_data(64'h4d44000410000001); + + send_fifo_data_32(31'h34D1ED6F); + + \#100000; + + send_fifo_data(64'h4d44000410000000); + + send_fifo_data_32(31'h3010F0D8); + +////////////////////////////////////////////// + +之后验证fifo_wr_en fifo_wr_data[31:0]是否正确 + +![局部截取_20260109_211614](./变成两个udp,一个负责收一个负责发.assets/局部截取_20260109_211614.png) + + + +### 保证状态TOE转发正确 + + + + \#1000; + + send_toe_data(66'h10102030405060708,66'h2b1b2b3b4b5b6b7b8,66'h3c1c2c3c4c5c6c7c8,66'h0a1a2a3a4a5a6a7a8,4); + + \#5000; + +之后验证fifo_wr_en_TOE fifo_wr_data_TOE[31:0]是否正确 + +![局部截取_20260109_211301](./变成两个udp,一个负责收一个负责发.assets/局部截取_20260109_211301.png) + +成功！ + +## udp_data_process + +![局部截取_20260109_214254](./变成两个udp,一个负责收一个负责发.assets/局部截取_20260109_214254.png) + +成功！ \ No newline at end of file diff --git a/status_to_udp.v b/status_to_udp.v index 34e2abc..32968d5 100644 --- a/status_to_udp.v +++ b/status_to_udp.v @@ -22,12 +22,18 @@ module status_to_udp ( input DAQ_Status_Info_valid, input DAQ_Status_Info_last, input [31:0] DAQ_Status_Info_data, + + // UDP0发送FIFO接口（负责TOE） + input udp_app_send_fifo_rden_0, + output [7:0] udp_app_send_fifo_rddata_0, + output [11:0] udp_app_send_fifo_rdcnt_0, + output udp_app_send_fifo_empty_0, - // UDP发送FIFO接口 - input udp_app_send_fifo_rden, - output [7:0] udp_app_send_fifo_rddata, - output [11:0] udp_app_send_fifo_rdcnt, - output udp_app_send_fifo_empty + // UDP1发送FIFO接口（负责3块板子） + input udp_app_send_fifo_rden_1, + output [7:0] udp_app_send_fifo_rddata_1, + output [11:0] udp_app_send_fifo_rdcnt_1, + output udp_app_send_fifo_empty_1 ); // =========================== 参数定义 =========================== @@ -42,15 +48,16 @@ localparam RECV_XYZ = 4'd6; localparam WAIT_DAQ_VALID = 4'd7; // 新增：等待DAQ valid localparam RECV_DAQ = 4'd8; -reg [2:0] S_state; -localparam SEND_IDLE = 3'd0; -localparam SEND_TOE_HEAD_LENGTH = 3'd1; -localparam SEND_TOE_DATA_1 = 3'd2; -localparam SEND_TOE_DATA_LENGTH = 3'd3; -localparam SEND_TOE_DATA_2 = 3'd4; -localparam SEND_CRC = 3'd5; -localparam SEND_INFO_HEAD_LENGTH = 3'd6; -localparam SEND_INFO_DATA = 3'd7; +reg [3:0] S_state; +localparam SEND_IDLE = 4'd0; +localparam SEND_TOE_HEAD_LENGTH = 4'd1; +localparam SEND_TOE_DATA_1 = 4'd2; +localparam SEND_TOE_DATA_LENGTH = 4'd3; +localparam SEND_TOE_DATA_2 = 4'd4; +localparam SEND_CRC_TOE = 4'd5; +localparam SEND_INFO_HEAD_LENGTH = 4'd6; +localparam SEND_INFO_DATA = 4'd7; +localparam SEND_CRC_INFO = 4'd8; // =========================== 寄存器定义 =========================== reg [31:0] data_buffer; @@ -58,9 +65,11 @@ reg [1:0] byte_counter; reg buffer_valid; // FIFO相关信号 -reg fifo_wr_en; +reg fifo_wr_en; //udp1 reg [31:0] fifo_wr_data; -wire fifo_full; +reg fifo_wr_en_TOE; //udp0 +reg [31:0] fifo_wr_data_TOE; + wire TOE_rec_fifo_empty; reg TOE_rec_fifo_rden; wire [65:0] TOE_rec_fifo_dout; @@ -89,20 +98,37 @@ wire [31:0] info_cache_fifo_dout; wire info_cache_fifo_full; wire info_cache_fifo_empty; -// =========================== FIFO实例化 =========================== +// =========================== FIFO =========================== -//512 depth 32to8 -fifo_generator_32to8 fifo_32to8 ( +//512 depth 32to8 --responsible for UDP0(TOE) +fifo_generator_32to8 fifo_32to8_TOE ( + .clk(clk), // input wire clk + .rst(reset), // input wire rst + .wr_en(fifo_wr_en_TOE), // input wire wr_en + .din(fifo_wr_data_TOE), // input wire [31 : 0] din + .full(), // output wire full + + .rd_en(udp_app_send_fifo_rden_0), // input wire rd_en + .dout(udp_app_send_fifo_rddata_0), // output wire [7 : 0] dout + .empty(udp_app_send_fifo_empty_0), // output wire empty + .rd_data_count(udp_app_send_fifo_rdcnt_0), // output wire [11 : 0] rd_data_count + + .wr_rst_busy(), // output wire wr_rst_busy + .rd_rst_busy() // output wire rd_rst_busy +); + +//512 depth 32to8 --responsible for UDP1(state_info) +fifo_generator_32to8 fifo_32to8_INFO ( .clk(clk), // input wire clk .rst(reset), // input wire rst .wr_en(fifo_wr_en), // input wire wr_en .din(fifo_wr_data), // input wire [31 : 0] din - .full(fifo_full), // output wire full + .full(), // output wire full - .rd_en(udp_app_send_fifo_rden), // input wire rd_en - .dout(udp_app_send_fifo_rddata), // output wire [7 : 0] dout - .empty(udp_app_send_fifo_empty), // output wire empty - .rd_data_count(udp_app_send_fifo_rdcnt), // output wire [11 : 0] rd_data_count + .rd_en(udp_app_send_fifo_rden_1), // input wire rd_en + .dout(udp_app_send_fifo_rddata_1), // output wire [7 : 0] dout + .empty(udp_app_send_fifo_empty_1), // output wire empty + .rd_data_count(udp_app_send_fifo_rdcnt_1), // output wire [11 : 0] rd_data_count .wr_rst_busy(), // output wire wr_rst_busy .rd_rst_busy() // output wire rd_rst_busy @@ -364,6 +390,8 @@ always @(posedge clk or posedge reset) begin S_state <= SEND_IDLE; fifo_wr_en <= 1'b0; fifo_wr_data <= 32'b0; + fifo_wr_en_TOE <= 1'b0;//udp0 + fifo_wr_data_TOE <= 32'b0; crc32_calc <= 32'hFFFFFFFF; info_cache_fifo_rden <= 1'b0; TOE_payload <= 64'b0; @@ -374,6 +402,8 @@ always @(posedge clk or posedge reset) begin SEND_IDLE: begin //0 fifo_wr_en <= 1'b0; fifo_wr_data <= 32'b0; + fifo_wr_en_TOE <= 1'b0;//udp0 + fifo_wr_data_TOE <= 32'b0; crc32_calc <= 32'hFFFFFFFF; send_finish <= 1'b0; Info_data_bytes_num_reg <= 1'b0; @@ -390,35 +420,35 @@ always @(posedge clk or posedge reset) begin end SEND_TOE_HEAD_LENGTH: begin //1 - fifo_wr_en <= 1'b1; - fifo_wr_data <= 32'h4547000c; + fifo_wr_en_TOE <= 1'b1; + fifo_wr_data_TOE <= 32'h4547000c; S_state <= SEND_TOE_DATA_1; end SEND_TOE_DATA_1: begin //2 - fifo_wr_en <= 1'b1; - fifo_wr_data <= TOE_payload[63:32]; + fifo_wr_en_TOE <= 1'b1; + fifo_wr_data_TOE <= TOE_payload[63:32]; crc32_calc <= calc_crc32(TOE_payload[63:32], crc32_calc); S_state <= SEND_TOE_DATA_LENGTH; end SEND_TOE_DATA_LENGTH: begin //3 - fifo_wr_en <= 1'b1; - fifo_wr_data <= 32'd4; // 固定四字节长度 + fifo_wr_en_TOE <= 1'b1; + fifo_wr_data_TOE <= 32'd4; // 固定四字节长度 crc32_calc <= calc_crc32(32'd4, crc32_calc); S_state <= SEND_TOE_DATA_2; end SEND_TOE_DATA_2: begin //4 - fifo_wr_en <= 1'b1; - fifo_wr_data <= TOE_payload[31:0]; + fifo_wr_en_TOE <= 1'b1; + fifo_wr_data_TOE <= TOE_payload[31:0]; crc32_calc <= calc_crc32(TOE_payload[31:0], crc32_calc); - S_state <= SEND_CRC; + S_state <= SEND_CRC_TOE; end - SEND_CRC: begin //5 - fifo_wr_en <= 1'b1; - fifo_wr_data <= crc32_calc; + SEND_CRC_TOE: begin //5 + fifo_wr_en_TOE <= 1'b1; + fifo_wr_data_TOE <= crc32_calc; S_state <= SEND_IDLE; send_finish <= 1'b1; info_cache_fifo_rden <= 1'b0; @@ -439,11 +469,20 @@ always @(posedge clk or posedge reset) begin if(info_cache_fifo_empty) begin info_cache_fifo_rden <= 1'b0; - S_state <= SEND_CRC; + S_state <= SEND_CRC_INFO; end else begin info_cache_fifo_rden <= 1'b1; end end + + SEND_CRC_INFO: begin //8 + fifo_wr_en <= 1'b1; + fifo_wr_data <= crc32_calc; + S_state <= SEND_IDLE; + send_finish <= 1'b1; + info_cache_fifo_rden <= 1'b0; + end + default: S_state <= SEND_IDLE; endcase