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UDP_data_process
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彻底修复因valid有时拉高有时拉低导致我的模块多发的问题，修复crc会计算包头的BUG

This commit is contained in:
yangshenbo 2026-01-09 19:42:43 +08:00
parent c8319dfb37
commit 40ed349fec
1 changed files with 7 additions and 2 deletions
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9
status_to_udp.v
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@ -268,8 +268,9 @@ always @(posedge clk) begin
if(CMU_Status_Info_valid) info_cache_fifo_wren <= 1'b1; if(CMU_Status_Info_valid) info_cache_fifo_wren <= 1'b1;
else info_cache_fifo_wren <= 1'b0; else info_cache_fifo_wren <= 1'b0;
info_cache_fifo_din <= CMU_Status_Info_data; info_cache_fifo_din <= CMU_Status_Info_data;
if (CMU_Status_Info_valid) begin /////valid可能为高低高低交替，所以计数也要加判断逻辑，以免多计数。
Info_data_bytes_num <= Info_data_bytes_num + 4; Info_data_bytes_num <= Info_data_bytes_num + 4;
end
if (CMU_Status_Info_last) begin if (CMU_Status_Info_last) begin
A_state <= IDLE; A_state <= IDLE;
CMU_Status_Info_ready <= 1'b0; CMU_Status_Info_ready <= 1'b0;
@ -302,7 +303,9 @@ always @(posedge clk) begin
if(XYZ_Status_Info_valid) info_cache_fifo_wren <= 1'b1; if(XYZ_Status_Info_valid) info_cache_fifo_wren <= 1'b1;
else info_cache_fifo_wren <= 1'b0; else info_cache_fifo_wren <= 1'b0;
info_cache_fifo_din <= XYZ_Status_Info_data; info_cache_fifo_din <= XYZ_Status_Info_data;
if (XYZ_Status_Info_valid) begin /////valid可能为高低高低交替，所以计数也要加判断逻辑，以免多计数。
Info_data_bytes_num <= Info_data_bytes_num + 4; Info_data_bytes_num <= Info_data_bytes_num + 4;
end
if (XYZ_Status_Info_last) begin if (XYZ_Status_Info_last) begin
A_state <= IDLE; A_state <= IDLE;
@ -336,7 +339,9 @@ always @(posedge clk) begin
if(DAQ_Status_Info_valid) info_cache_fifo_wren <= 1'b1; if(DAQ_Status_Info_valid) info_cache_fifo_wren <= 1'b1;
else info_cache_fifo_wren <= 1'b0; else info_cache_fifo_wren <= 1'b0;
info_cache_fifo_din <= DAQ_Status_Info_data; info_cache_fifo_din <= DAQ_Status_Info_data;
if (DAQ_Status_Info_valid) begin /////valid可能为高低高低交替，所以计数也要加判断逻辑，以免多计数。
Info_data_bytes_num <= Info_data_bytes_num + 4; Info_data_bytes_num <= Info_data_bytes_num + 4;
end
if (DAQ_Status_Info_last) begin if (DAQ_Status_Info_last) begin
A_state <= IDLE; A_state <= IDLE;
@ -423,7 +428,7 @@ always @(posedge clk or posedge reset) begin
fifo_wr_en <= 1'b1; fifo_wr_en <= 1'b1;
fifo_wr_data[31:16] <= 16'h494e; // "IN" fifo_wr_data[31:16] <= 16'h494e; // "IN"
fifo_wr_data[15:0] <= Info_data_bytes_num_reg; fifo_wr_data[15:0] <= Info_data_bytes_num_reg;
crc32_calc <= calc_crc32({16'h494e, Info_data_bytes_num_reg}, 32'hFFFFFFFF); crc32_calc <= 32'hFFFFFFFF; //be ready to caculate crc
S_state <= SEND_INFO_DATA; S_state <= SEND_INFO_DATA;
end end