UDP_data_process/try_smg/counter.v

module counter
(
    input clk, enable, rst_n,
    output reg [8-1:0] count
);

always @ (posedge clk or negedge rst_n)
begin
    if (!rst_n)
        count <= 0;
    else if (enable == 1'b1)
        count <= count + 1;
end
endmodule