15 lines
247 B
Coq
15 lines
247 B
Coq
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module counter
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(
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input clk, enable, rst_n,
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output reg [8-1:0] count
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);
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always @ (posedge clk or negedge rst_n)
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begin
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if (!rst_n)
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count <= 0;
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else if (enable == 1'b1)
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count <= count + 1;
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end
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endmodule
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