• Joined on 2024-02-19
thfu pushed to main at thfu/TailCorr 2024-11-09 17:13:33 +08:00
8fa46ded3a v04-IIR based on IP core
thfu pushed to main at thfu/TailCorr 2024-11-07 10:58:29 +08:00
e757bd72c6 Enable of clk_div2 tested on FPGA
thfu pushed to main at thfu/TailCorr 2024-11-04 19:09:57 +08:00
b00693ce73 choose the min length to compare
thfu pushed to main at thfu/TailCorr 2024-11-04 19:07:47 +08:00
2fdaaa3611 Fit modification of enable signal as clk divided by 2
thfu pushed to main at thfu/TailCorr 2024-11-04 19:03:30 +08:00
da3157a7d8 Modify enable signal as clk divided by 2
thfu pushed to main at thfu/TailCorr 2024-10-17 17:31:51 +08:00
85b2d97c02 modify relevant .v file and .m file to verify the accuracy of rtl code
thfu pushed to main at thfu/TailCorr 2024-10-08 17:58:49 +08:00
7a1c7f3523 add verification code of matlab
thfu pushed to main at thfu/TailCorr 2024-10-08 11:43:12 +08:00
df1da34c44 only add makefile and filelist in sim
thfu pushed to main at thfu/TailCorr 2024-10-08 11:38:25 +08:00
fa9fc93456 delete sim file,there is too many temporary file
thfu pushed to main at thfu/TailCorr 2024-10-08 11:34:38 +08:00
1dcfdbd76a delete repeated .v file
thfu pushed to main at thfu/TailCorr 2024-10-08 11:27:55 +08:00
c6ff7dc280 add 8 interpolation
thfu deleted branch master from thfu/TailCorr 2024-10-08 10:38:29 +08:00
thfu created branch master in thfu/TailCorr 2024-10-08 10:29:21 +08:00
thfu pushed to master at thfu/TailCorr 2024-10-08 10:29:21 +08:00
3a0f3346b0 add 8 interpolation
thfu renamed repository from xyz-chip to thfu/TailCorr 2024-04-16 10:17:51 +08:00
thfu created branch main in thfu/TailCorr 2024-04-16 10:15:29 +08:00
thfu pushed to main at thfu/TailCorr 2024-04-16 10:15:29 +08:00
dcd8166010 init
thfu created repository thfu/TailCorr 2024-04-16 10:05:39 +08:00