thfu
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  • Joined on 2024-02-19
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thfu pushed to MyIIR at thfu/TailCorr 2025-03-08 13:55:29 +08:00
900c042f75 add coefficient generation module and z_dsp; remove interpolation module and other files; suggest further simplification of RTL code using for-loops
thfu pushed to MyIIR at thfu/TailCorr 2025-03-08 11:35:49 +08:00
49f1d2e44d add coefficient generation module and z_dsp; remove interpolation module and other files; suggest further simplification of RTL code using for-loops
thfu pushed to MyIIR at thfu/TailCorr 2025-03-03 18:10:19 +08:00
e42378b1ab An eight-channel parallel IIR filter, with the on-chip coefficient generation module yet to be developed, and no for loops used.
thfu pushed to main at thfu/TailCorr 2025-02-26 16:05:36 +08:00
thfu pushed to MyIIR at thfu/TailCorr 2025-02-26 16:02:29 +08:00
f547d17650 原脚本太长，将其划分为不同功能模块并进行封装管理
6e1218e622 修改z_dsp.m相关函数以批量扫描线路参数和波形
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thfu pushed to MyIIR at thfu/TailCorr 2025-02-26 15:51:05 +08:00
2861f02533 Á½Â·²¢ÐеÄIIRÂ˲¨Æ÷£¬ÏÂÒ»²½¸ÄÖÁ°Ë·²¢ÐÐ
thfu pushed to main at thfu/TailCorr 2024-12-23 20:27:45 +08:00
a7796239c8 删除了Z芯片的SRAM文件夹；
thfu pushed to main at thfu/TailCorr 2024-11-28 17:48:32 +08:00
52efa3a769 v04-modify parameter position
thfu pushed to main at thfu/TailCorr 2024-11-28 17:46:49 +08:00
thfu pushed to main at thfu/TailCorr 2024-11-28 17:19:23 +08:00
aba2785320 v04-modify parameter position
thfu pushed to main at thfu/TailCorr 2024-11-27 16:35:33 +08:00
cbf8ab957e v04-using DW_iir_dc_m.v;TB don't use ca_wave
thfu pushed to main at thfu/TailCorr 2024-11-27 16:26:19 +08:00
ee9c217328 v01-using DW_iir_dc_m.v;TB don't use cs_wave
thfu pushed to main at thfu/TailCorr 2024-11-27 10:06:45 +08:00
7a9171d964 v04-MeanIntp_8 with FixRound;Modify the directory structure
thfu pushed to MyIIR at thfu/TailCorr 2024-11-26 22:57:27 +08:00
a7b7faf8df v01-modiy absolute path in z_dsp.m
thfu pushed to main at thfu/TailCorr 2024-11-26 21:00:06 +08:00
334a19edec v04-z_dsp 4 ports output
thfu pushed to MyIIR at thfu/TailCorr 2024-11-26 20:38:42 +08:00
9dcfcd4028 v01-.v files convert reg to wire;.m files include diff and sqt both less than 1e-4
thfu pushed to MyIIR at thfu/TailCorr 2024-11-26 17:57:36 +08:00
456a9fb479 v01-z_dsp delay width debug;add z_dsp.m add diff_plot_py.m
thfu pushed to MyIIR at thfu/TailCorr 2024-11-26 17:50:42 +08:00
958c88638e z_dsp delay width debug;add z_dsp.m and diff_plot_py.m
thfu pushed to MyIIR at thfu/TailCorr 2024-11-26 13:34:36 +08:00
5cd9b46a21 v01-add round module;intp8 and mult_C using round;Modify the directory structure
thfu pushed to MyIIR at thfu/TailCorr 2024-11-25 23:05:53 +08:00
6908587dae v01-enable of clk_div2;8pin to 4pin;valid I/O