143 lines
3.4 KiB
Verilog
143 lines
3.4 KiB
Verilog
module TB();
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initial
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begin
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$fsdbDumpfile("TB.fsdb");
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$fsdbDumpvars(0, TB);
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end
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reg clk;
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reg rstn;
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reg en;
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reg [21:0] cnt;
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initial begin
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#0;
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rstn = 1'b0;
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clk = 1'b0;
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en = 1'b0;
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#300;
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rstn = 1'b1;
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end
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always #200 clk = ~clk;
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wire clk_div16_0;
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wire clk_div16_1;
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wire clk_div16_2;
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wire clk_div16_3;
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wire clk_div16_4;
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wire clk_div16_5;
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wire clk_div16_6;
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wire clk_div16_7;
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wire clk_div16_8;
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wire clk_div16_9;
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wire clk_div16_a;
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wire clk_div16_b;
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wire clk_div16_c;
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wire clk_div16_d;
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wire clk_div16_e;
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wire clk_div16_f;
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clk_gen inst_clk_gen(
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.rstn (rstn ),
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.clk (clk ),
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.clk_div16_0 (clk_div16_0 ),
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.clk_div16_1 (clk_div16_1 ),
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.clk_div16_2 (clk_div16_2 ),
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.clk_div16_3 (clk_div16_3 ),
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.clk_div16_4 (clk_div16_4 ),
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.clk_div16_5 (clk_div16_5 ),
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.clk_div16_6 (clk_div16_6 ),
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.clk_div16_7 (clk_div16_7 ),
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.clk_div16_8 (clk_div16_8 ),
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.clk_div16_9 (clk_div16_9 ),
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.clk_div16_a (clk_div16_a ),
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.clk_div16_b (clk_div16_b ),
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.clk_div16_c (clk_div16_c ),
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.clk_div16_d (clk_div16_d ),
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.clk_div16_e (clk_div16_e ),
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.clk_div16_f (clk_div16_f ),
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.clk_h (clk_h ),
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.clk_l (clk_l )
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);
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always@(posedge clk_div16_f or negedge rstn)
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if(!rstn)
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cnt <= 22'd0;
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else
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cnt <= cnt + 22'd1;
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initial begin
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wait(cnt[17]==1'b1)
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$finish(0);
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end
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always@(posedge clk_div16_f or negedge rstn)
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begin
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if(cnt >= 2047 )
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begin
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en <= 1'b1;
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end
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else
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begin
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en <= 1'b0;
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end
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end
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reg [47:0] fcw;
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initial begin
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fcw = 48'h0840_0000_0000;
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end
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wire [15:0] cos;
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wire [15:0] sin;
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NCO inst_nco_0(
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.clk (clk_div16_f ),
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.rstn (rstn ),
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.phase_manual_clr (1'b0 ),
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.phase_auto_clr (1'b0 ),
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.fcw (fcw ),
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.pha (16'd0 ),
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.cos (cos ),
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.sin (sin )
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);
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wire [15:0] dout_p0;
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wire [15:0] dout_p1;
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wire [15:0] dout_p2;
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wire [15:0] dout_p3;
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MeanIntp4 inst_MeanIntp4
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(
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.clk (clk_div16_f ),
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.rstn (rstn ),
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.en (en ),
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.din (cos & {16{en}} ),
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.dout4_0 (dout_p0 ),
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.dout4_1 (dout_p1 ),
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.dout4_2 (dout_p2 ),
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.dout4_3 (dout_p3 )
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);
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reg [15:0] cs_wave;
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always@(posedge clk_div16_e) cs_wave = dout_p0;
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always@(posedge clk_div16_a) cs_wave = dout_p1;
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always@(posedge clk_div16_6) cs_wave = dout_p2;
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always@(posedge clk_div16_2) cs_wave = dout_p3;
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endmodule
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