unknown e757bd72c6 Enable of clk_div2 tested on FPGA		2024-11-07 10:57:58 +08:00
..
nco	modify relevant .v file and .m file to verify the accuracy of rtl code	2024-10-17 17:29:11 +08:00
DW02_mult.v	add 8 interpolation	2024-10-08 11:24:32 +08:00
DW_mult_pipe.v	add 8 interpolation	2024-10-08 11:24:32 +08:00
IIR_Filter.v	add 8 interpolation	2024-10-08 11:24:32 +08:00
MeanIntp_8.v	modify relevant .v file and .m file to verify the accuracy of rtl code	2024-10-17 17:29:11 +08:00
TailCorr_top.v	add 8 interpolation	2024-10-08 11:24:32 +08:00
diff.v	add 8 interpolation	2024-10-08 11:24:32 +08:00
lsdacif.v	modify relevant .v file and .m file to verify the accuracy of rtl code	2024-10-17 17:29:11 +08:00
mult_C.v	add 8 interpolation	2024-10-08 11:24:32 +08:00
z_data_mux.v	add 8 interpolation	2024-10-08 11:24:32 +08:00
z_dsp.v	Fit modification of enable signal as clk divided by 2	2024-11-04 19:07:35 +08:00
z_dsp_en_Test.v	Enable of clk_div2 tested on FPGA	2024-11-07 10:57:58 +08:00