thfu
/
TailCorr
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
拖尾矫正
11 Commits 4 Branches 0 Tags 22 MiB
Verilog 80.6%
SystemVerilog 13.1%
MATLAB 3.5%
Coq 1.2%
Makefile 1.1%
Other 0.5%
Go to file
unknown e757bd72c6 Enable of clk_div2 tested on FPGA 2024-11-07 10:57:58 +08:00
rtl Enable of clk_div2 tested on FPGA 2024-11-07 10:57:58 +08:00
script_m choose the min length to compare 2024-11-04 19:09:41 +08:00
sim Fit modification of enable signal as clk divided by 2 2024-11-04 19:07:35 +08:00
tb Fit modification of enable signal as clk divided by 2 2024-11-04 19:07:35 +08:00