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thfu e058191d12 Modify enable signal as clk divided by 2 
使能口连时钟二分频；
diff_plot.m使用最短的进行对比

Fit modification of enable signal as clk divided by 2

choose the min length to compare

Enable of clk_div2 tested on FPGA
 		2025-03-11 19:38:34 +08:00
..
MeanIntp.m 增加了八倍内插模块； 2025-03-11 19:36:24 +08:00
MyIIR.m 增加了八倍内插模块； 2025-03-11 19:36:24 +08:00
MyIIR_test.m 增加了八倍内插模块； 2025-03-11 19:36:24 +08:00
PolyMean_Test.m 增加了八倍内插模块； 2025-03-11 19:36:24 +08:00
TailCorr.m 增加了八倍内插模块； 2025-03-11 19:36:24 +08:00
TailCorr_8inpt_test.m 增加了八倍内插模块； 2025-03-11 19:36:24 +08:00
TailCorr_test.m 增加了八倍内插模块； 2025-03-11 19:36:24 +08:00
TailCorr_test_P.m 增加了八倍内插模块； 2025-03-11 19:36:24 +08:00
diff_plot.m Modify enable signal as clk divided by 2 2025-03-11 19:38:34 +08:00
intp8_Test.m 增加了八倍内插模块； 2025-03-11 19:36:24 +08:00