269 lines
6.4 KiB
Verilog
269 lines
6.4 KiB
Verilog
//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : TailCorr_top.v
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// Department :
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// Author : thfu
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.3 2024-05-15 thfu
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module TailCorr_top
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(
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clk,
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rstn,
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en,
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tc_bypass,
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din_re,
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din_im,
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a0_re,
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a0_im,
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b0_re,
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b0_im,
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a1_re,
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a1_im,
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b1_re,
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b1_im,
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a2_re,
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a2_im,
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b2_re,
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b2_im,
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a3_re,
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a3_im,
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b3_re,
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b3_im,
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a4_re,
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a4_im,
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b4_re,
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b4_im,
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a5_re,
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a5_im,
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b5_re,
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b5_im,
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dout
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);
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input rstn;
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input clk;
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input en;
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input tc_bypass;
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input signed [15:0] din_re;
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input signed [15:0] din_im;
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input signed [36:0] a0_re;
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input signed [36:0] a0_im;
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input signed [20:0] b0_re;
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input signed [20:0] b0_im;
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input signed [36:0] a1_re;
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input signed [36:0] a1_im;
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input signed [20:0] b1_re;
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input signed [20:0] b1_im;
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input signed [36:0] a2_re;
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input signed [36:0] a2_im;
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input signed [20:0] b2_re;
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input signed [20:0] b2_im;
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input signed [36:0] a3_re;
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input signed [36:0] a3_im;
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input signed [20:0] b3_re;
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input signed [20:0] b3_im;
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input signed [36:0] a4_re;
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input signed [36:0] a4_im;
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input signed [20:0] b4_re;
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input signed [20:0] b4_im;
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input signed [36:0] a5_re;
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input signed [36:0] a5_im;
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input signed [20:0] b5_re;
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input signed [20:0] b5_im;
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output signed [15:0] dout;
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wire signed [15:0] IIRin_re;
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wire signed [15:0] IIRin_im;
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wire signed [15:0] dout_0;
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wire signed [15:0] dout_1;
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wire signed [15:0] dout_2;
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wire signed [15:0] dout_3;
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wire signed [15:0] dout_4;
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wire signed [15:0] dout_5;
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wire signed [18:0] Ysum;
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reg signed [15:0] din_r0;
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reg signed [15:0] din_r1;
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reg signed [15:0] din_r2;
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reg signed [15:0] din_r3;
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reg signed [15:0] din_r4;
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reg signed [15:0] dout_r;
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diff inst_diffRe
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(
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.din (din_re ),
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.dout (IIRin_re )
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);
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diff inst_diffIm
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(
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.din (din_im ),
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.dout (IIRin_im )
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);
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IIR_Filter inst_iir_0 (
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.din_re (IIRin_re ),
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.din_im (IIRin_im ),
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.a_re (a0_re ),
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.a_im (a0_im ),
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.b_re (b0_re ),
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.b_im (b0_im ),
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.dout (dout_0 )
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);
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IIR_Filter inst_iir_1 (
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.din_re (IIRin_re ),
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.din_im (IIRin_im ),
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.a_re (a1_re ),
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.a_im (a1_im ),
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.b_re (b1_re ),
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.b_im (b1_im ),
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.dout (dout_1 )
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);
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IIR_Filter inst_iir_2 (
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.din_re (IIRin_re ),
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.din_im (IIRin_im ),
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.a_re (a2_re ),
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.a_im (a2_im ),
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.b_re (b2_re ),
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.b_im (b2_im ),
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.dout (dout_2 )
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);
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IIR_Filter inst_iir_3 (
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.din_re (IIRin_re ),
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.din_im (IIRin_im ),
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.a_re (a3_re ),
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.a_im (a3_im ),
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.b_re (b3_re ),
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.b_im (b3_im ),
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.dout (dout_3 )
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);
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IIR_Filter inst_iir_4 (
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.din_re (IIRin_re ),
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.din_im (IIRin_im ),
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.a_re (a4_re ),
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.a_im (a4_im ),
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.b_re (b4_re ),
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.b_im (b4_im ),
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.dout (dout_4 )
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);
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IIR_Filter inst_iir_5 (
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.din_re (IIRin_re ),
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.din_im (IIRin_im ),
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.a_re (a5_re ),
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.a_im (a5_im ),
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.b_re (b5_re ),
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.b_im (b5_im ),
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.dout (dout_5 )
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);
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always @(posedge clk or negedge rstn)
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if (!rstn)
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begin
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din_r0 <= 'h0;
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din_r1 <= 'h0;
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din_r2 <= 'h0;
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din_r3 <= 'h0;
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din_r4 <= 'h0;
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end
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else if(en)
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begin
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din_r0 <= din_re;
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din_r1 <= din_r0;
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din_r2 <= din_r1;
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din_r3 <= din_r2;
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din_r4 <= din_r3;
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end
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else
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begin
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din_r0 <= din_r0;
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din_r1 <= din_r1;
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din_r2 <= din_r2;
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din_r3 <= din_r3;
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din_r4 <= din_r4;
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end
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assign Ysum = dout_0 + dout_1 + dout_2 + dout_3 + dout_4 + dout_5 + din_r4;
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always@(posedge clk or negedge rstn)
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if (!rstn)begin
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dout_r <= 'h0;
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end
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else if(tc_bypass)begin
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dout_r <= din_re;
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end
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else begin
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if(en)begin
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if(Ysum[16:15]==2'b01)
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dout_r <= 16'd32767;
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else if(Ysum[16:15]==2'b10)
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dout_r <= -16'd32768;
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else
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dout_r <= Ysum[15:0];
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end
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else begin
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dout_r <= dout_r;
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end
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end
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assign dout = dout_r;
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endmodule
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