thfu e058191d12 Modify enable signal as clk divided by 2 ... 使能口连时钟二分频； diff_plot.m使用最短的进行对比 Fit modification of enable signal as clk divided by 2 choose the min length to compare Enable of clk_div2 tested on FPGA		2025-03-11 19:38:34 +08:00
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nco	增加了八倍内插模块；	2025-03-11 19:36:24 +08:00
DW02_mult.v	增加了八倍内插模块；	2025-03-11 19:36:24 +08:00
DW_mult_pipe.v	增加了八倍内插模块；	2025-03-11 19:36:24 +08:00
IIR_Filter.v	增加了八倍内插模块；	2025-03-11 19:36:24 +08:00
MeanIntp_8.v	增加了八倍内插模块；	2025-03-11 19:36:24 +08:00
TailCorr_top.v	增加了八倍内插模块；	2025-03-11 19:36:24 +08:00
diff.v	增加了八倍内插模块；	2025-03-11 19:36:24 +08:00
lsdacif.v	增加了八倍内插模块；	2025-03-11 19:36:24 +08:00
mult_C.v	增加了八倍内插模块；	2025-03-11 19:36:24 +08:00
z_data_mux.v	增加了八倍内插模块；	2025-03-11 19:36:24 +08:00
z_dsp.v	Modify enable signal as clk divided by 2	2025-03-11 19:38:34 +08:00
z_dsp_en_Test.v	Modify enable signal as clk divided by 2	2025-03-11 19:38:34 +08:00