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拖尾矫正
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thfu e058191d12 Modify enable signal as clk divided by 2 
使能口连时钟二分频；
diff_plot.m使用最短的进行对比

Fit modification of enable signal as clk divided by 2

choose the min length to compare

Enable of clk_div2 tested on FPGA
 		2025-03-11 19:38:34 +08:00
rtl Modify enable signal as clk divided by 2 2025-03-11 19:38:34 +08:00
script_m Modify enable signal as clk divided by 2 2025-03-11 19:38:34 +08:00
sim Modify enable signal as clk divided by 2 2025-03-11 19:38:34 +08:00
tb Modify enable signal as clk divided by 2 2025-03-11 19:38:34 +08:00