53 lines
1.0 KiB
Verilog
53 lines
1.0 KiB
Verilog
module mult_C(
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a,
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b,
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c,
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d,
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Re,
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Im
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);
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parameter integer A_width = 8;
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parameter integer B_width = 8;
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parameter integer C_width = 8;
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parameter integer D_width = 8;
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input signed [A_width-1:0] a;
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input signed [B_width-1:0] b;
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input signed [C_width-1:0] c;
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input signed [D_width-1:0] d;
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output signed [A_width+C_width:0] Re;
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output signed [A_width+D_width:0] Im;
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wire signed [A_width+C_width-1:0] ac;
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wire signed [B_width+D_width-1:0] bd;
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wire signed [A_width+D_width-1:0] ad;
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wire signed [B_width+C_width-1:0] bc;
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DW02_mult #(A_width,C_width) inst_c1( .A (a ),
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.B (c ),
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.TC (1'b1 ),
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.PRODUCT (ac )
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);
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DW02_mult #(B_width,D_width) inst_c2( .A (b ),
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.B (d ),
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.TC (1'b1 ),
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.PRODUCT (bd )
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);
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DW02_mult #(A_width,D_width) inst_c3( .A (a ),
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.B (d ),
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.TC (1'b1 ),
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.PRODUCT (ad )
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);
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DW02_mult #(B_width,C_width) inst_c4( .A (b ),
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.B (c ),
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.TC (1'b1 ),
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.PRODUCT (bc )
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);
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assign Re = ac - bd;
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assign Im = ad + bc;
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endmodule |