37 lines
458 B
Verilog
37 lines
458 B
Verilog
module diff(
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clk,
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rstn,
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din,
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dout
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);
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input rstn;
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input clk;
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input signed [15:0] din;
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output signed [15:0] dout;
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reg [15:0] din_r;
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reg [15:0] din_r1;
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reg [15:0] out_r;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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begin
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din_r <= 16'd0;
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din_r1 <= 16'd0;
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out_r <= 16'd0;
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end
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else
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begin
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din_r <= din;
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din_r1 <= din_r;
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out_r <= din_r - din_r1;
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end
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assign dout = out_r;
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endmodule |