287 lines
8.7 KiB
Verilog
287 lines
8.7 KiB
Verilog
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`timescale 1 ns/1 ns
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module TB();
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initial
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begin
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$fsdbDumpfile("TB.fsdb");
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$fsdbDumpvars(0, TB);
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$fsdbDumpMDA();
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end
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reg clk ;
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reg en;
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reg [5:0] vldi;
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reg rst_n;
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reg signed [31:0] a_re [5:0];
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reg signed [31:0] a_im [5:0];
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reg signed [31:0] b_re [5:0];
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reg signed [31:0] b_im [5:0];
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wire signed [31:0] ao_re [5:0];
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wire signed [31:0] ao_im [5:0];
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wire signed [31:0] ab_re [5:0];
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wire signed [31:0] ab_im [5:0];
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wire signed [31:0] abb_re [5:0];
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wire signed [31:0] abb_im [5:0];
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wire signed [31:0] ab_pow3_re [5:0];
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wire signed [31:0] ab_pow3_im [5:0];
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wire signed [31:0] ab_pow4_re [5:0];
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wire signed [31:0] ab_pow4_im [5:0];
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wire signed [31:0] ab_pow5_re [5:0];
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wire signed [31:0] ab_pow5_im [5:0];
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wire signed [31:0] ab_pow6_re [5:0];
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wire signed [31:0] ab_pow6_im [5:0];
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wire signed [31:0] ab_pow7_re [5:0];
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wire signed [31:0] ab_pow7_im [5:0];
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wire signed [31:0] bo_re [5:0];
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wire signed [31:0] bo_im [5:0];
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wire signed [31:0] b_pow8_re [5:0];
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wire signed [31:0] b_pow8_im [5:0];
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parameter CYCLE = 20;
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parameter RST_TIME = 3 ;
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CoefGen inst_CoefGen(
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.clk (clk ),
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.rstn (rst_n ),
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.vldi (vldi ),
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.a0_re (a_re[0] ),
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.a0_im (a_im[0] ),
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.b0_re (b_re[0] ),
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.b0_im (b_im[0] ),
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.a1_re (a_re[1] ),
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.a1_im (a_im[1] ),
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.b1_re (b_re[1] ),
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.b1_im (b_im[1] ),
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.a2_re (a_re[2] ),
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.a2_im (a_im[2] ),
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.b2_re (b_re[2] ),
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.b2_im (b_im[2] ),
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.a3_re (a_re[3] ),
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.a3_im (a_im[3] ),
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.b3_re (b_re[3] ),
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.b3_im (b_im[3] ),
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.a4_re (a_re[4] ),
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.a4_im (a_im[4] ),
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.b4_re (b_re[4] ),
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.b4_im (b_im[4] ),
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.a5_re (a_re[5] ),
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.a5_im (a_im[5] ),
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.b5_re (b_re[5] ),
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.b5_im (b_im[5] ),
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.a_re0 (ao_re[0] ),
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.a_im0 (ao_im[0] ),
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.b_re0 (bo_re[0] ),
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.b_im0 (bo_im[0] ),
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.ab_re0 (ab_re[0] ),
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.ab_im0 (ab_im[0] ),
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.abb_re0 (abb_re[0] ),
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.abb_im0 (abb_im[0] ),
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.ab_pow3_re0 (ab_pow3_re[0]),
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.ab_pow3_im0 (ab_pow3_im[0]),
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.ab_pow4_re0 (ab_pow4_re[0]),
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.ab_pow4_im0 (ab_pow4_im[0]),
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.ab_pow5_re0 (ab_pow5_re[0]),
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.ab_pow5_im0 (ab_pow5_im[0]),
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.ab_pow6_re0 (ab_pow6_re[0]),
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.ab_pow6_im0 (ab_pow6_im[0]),
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.ab_pow7_re0 (ab_pow7_re[0]),
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.ab_pow7_im0 (ab_pow7_im[0]),
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.b_pow8_re0 (b_pow8_re[0] ),
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.b_pow8_im0 (b_pow8_im[0] ),
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.a_re1 (ao_re[1] ),
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.a_im1 (ao_im[1] ),
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.b_re1 (bo_re[1] ),
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.b_im1 (bo_im[1] ),
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.ab_re1 (ab_re[1] ),
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.ab_im1 (ab_im[1] ),
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.abb_re1 (abb_re[1] ),
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.abb_im1 (abb_im[1] ),
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.ab_pow3_re1 (ab_pow3_re[1]),
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.ab_pow3_im1 (ab_pow3_im[1]),
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.ab_pow4_re1 (ab_pow4_re[1]),
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.ab_pow4_im1 (ab_pow4_im[1]),
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.ab_pow5_re1 (ab_pow5_re[1]),
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.ab_pow5_im1 (ab_pow5_im[1]),
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.ab_pow6_re1 (ab_pow6_re[1]),
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.ab_pow6_im1 (ab_pow6_im[1]),
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.ab_pow7_re1 (ab_pow7_re[1]),
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.ab_pow7_im1 (ab_pow7_im[1]),
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.b_pow8_re1 (b_pow8_re[1] ),
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.b_pow8_im1 (b_pow8_im[1] ),
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.a_re2 (ao_re[2] ),
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.a_im2 (ao_im[2] ),
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.b_re2 (bo_re[2] ),
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.b_im2 (bo_im[2] ),
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.ab_re2 (ab_re[2] ),
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.ab_im2 (ab_im[2] ),
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.abb_re2 (abb_re[2] ),
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.abb_im2 (abb_im[2] ),
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.ab_pow3_re2 (ab_pow3_re[2]),
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.ab_pow3_im2 (ab_pow3_im[2]),
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.ab_pow4_re2 (ab_pow4_re[2]),
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.ab_pow4_im2 (ab_pow4_im[2]),
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.ab_pow5_re2 (ab_pow5_re[2]),
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.ab_pow5_im2 (ab_pow5_im[2]),
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.ab_pow6_re2 (ab_pow6_re[2]),
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.ab_pow6_im2 (ab_pow6_im[2]),
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.ab_pow7_re2 (ab_pow7_re[2]),
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.ab_pow7_im2 (ab_pow7_im[2]),
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.b_pow8_re2 (b_pow8_re[2] ),
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.b_pow8_im2 (b_pow8_im[2] ),
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.a_re3 (ao_re[3] ),
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.a_im3 (ao_im[3] ),
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.b_re3 (bo_re[3] ),
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.b_im3 (bo_im[3] ),
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.ab_re3 (ab_re[3] ),
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.ab_im3 (ab_im[3] ),
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.abb_re3 (abb_re[3] ),
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.abb_im3 (abb_im[3] ),
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.ab_pow3_re3 (ab_pow3_re[3]),
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.ab_pow3_im3 (ab_pow3_im[3]),
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.ab_pow4_re3 (ab_pow4_re[3]),
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.ab_pow4_im3 (ab_pow4_im[3]),
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.ab_pow5_re3 (ab_pow5_re[3]),
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.ab_pow5_im3 (ab_pow5_im[3]),
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.ab_pow6_re3 (ab_pow6_re[3]),
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.ab_pow6_im3 (ab_pow6_im[3]),
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.ab_pow7_re3 (ab_pow7_re[3]),
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.ab_pow7_im3 (ab_pow7_im[3]),
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.b_pow8_re3 (b_pow8_re[3] ),
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.b_pow8_im3 (b_pow8_im[3] ),
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.a_re4 (ao_re[4] ),
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.a_im4 (ao_im[4] ),
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.b_re4 (bo_re[4] ),
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.b_im4 (bo_im[4] ),
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.ab_re4 (ab_re[4] ),
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.ab_im4 (ab_im[4] ),
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.abb_re4 (abb_re[4] ),
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.abb_im4 (abb_im[4] ),
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.ab_pow3_re4 (ab_pow3_re[4]),
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.ab_pow3_im4 (ab_pow3_im[4]),
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.ab_pow4_re4 (ab_pow4_re[4]),
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.ab_pow4_im4 (ab_pow4_im[4]),
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.ab_pow5_re4 (ab_pow5_re[4]),
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.ab_pow5_im4 (ab_pow5_im[4]),
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.ab_pow6_re4 (ab_pow6_re[4]),
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.ab_pow6_im4 (ab_pow6_im[4]),
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.ab_pow7_re4 (ab_pow7_re[4]),
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.ab_pow7_im4 (ab_pow7_im[4]),
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.b_pow8_re4 (b_pow8_re[4] ),
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.b_pow8_im4 (b_pow8_im[4] ),
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.a_re5 (ao_re[5] ),
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.a_im5 (ao_im[5] ),
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.b_re5 (bo_re[5] ),
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.b_im5 (bo_im[5] ),
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.ab_re5 (ab_re[5] ),
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.ab_im5 (ab_im[5] ),
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.abb_re5 (abb_re[5] ),
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.abb_im5 (abb_im[5] ),
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.ab_pow3_re5 (ab_pow3_re[5]),
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.ab_pow3_im5 (ab_pow3_im[5]),
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.ab_pow4_re5 (ab_pow4_re[5]),
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.ab_pow4_im5 (ab_pow4_im[5]),
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.ab_pow5_re5 (ab_pow5_re[5]),
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.ab_pow5_im5 (ab_pow5_im[5]),
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.ab_pow6_re5 (ab_pow6_re[5]),
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.ab_pow6_im5 (ab_pow6_im[5]),
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.ab_pow7_re5 (ab_pow7_re[5]),
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.ab_pow7_im5 (ab_pow7_im[5]),
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.b_pow8_re5 (b_pow8_re[5] ),
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.b_pow8_im5 (b_pow8_im[5] )
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);
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initial begin
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clk = 0;
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forever
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#(CYCLE/2)
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clk=~clk;
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end
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reg [15:0] st1;
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reg [15:0] st2;
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reg [15:0] st3;
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reg [15:0] st4;
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initial begin
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rst_n = 0;
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vldi <= 0;
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st1 = 100;
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st2 = 101;
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st3 = 110;
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st4 = 111;
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repeat(3) @(posedge clk);
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vldi[0] <= 1;
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rst_n = 1;
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a_re[0] <= 55007237;
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a_im[0] <= 0;
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b_re[0] <= 2143083068;
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b_im[0] <= 0;
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@(posedge clk);
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vldi[0] <= 0;
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a_re[0] <= 0;
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a_im[0] <= 0;
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b_re[0] <= 0;
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b_im[0] <= 0;
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repeat(8) @(posedge clk);
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vldi[1] <= 1;
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rst_n = 1;
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a_re[1] <= 32690030;
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a_im[1] <= 0;
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b_re[1] <= 2145807236;
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b_im[1] <= 0;
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@(posedge clk);
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vldi[1] <= 0;
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a_re[1] <= 0;
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a_im[1] <= 0;
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b_re[1] <= 0;
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b_im[1] <= 0;
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repeat(8) @(posedge clk);
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vldi[2] <= 1;
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rst_n = 1;
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a_re[2] <= 429516;
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a_im[2] <= 0;
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b_re[2] <= 2146812530;
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b_im[2] <= 0;
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@(posedge clk);
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vldi[2] <= 0;
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a_re[2] <= 0;
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a_im[2] <= 0;
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b_re[2] <= 0;
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b_im[2] <= 0;
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end
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reg [21:0] cnt;
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always@(posedge clk or negedge rst_n)
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if(!rst_n) begin
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cnt <= 22'd0;
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end
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else begin
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cnt <= cnt + 22'd1;
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end
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initial
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begin
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wait(cnt[16]==1'b1)
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$finish(0);
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end
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endmodule
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