443 lines
14 KiB
Systemverilog
443 lines
14 KiB
Systemverilog
module CoefGen #(
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parameter data_in_width = 32
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,parameter coef_width = 32
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,parameter frac_data_out_width = 20//X for in,5
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,parameter frac_coef_width = 31//division
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)
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(
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input rstn
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,input clk
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,input [5:0] vldi
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,input signed [31:0] a0_re
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,input signed [31:0] b0_re
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,input signed [31:0] a1_re
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,input signed [31:0] b1_re
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,input signed [31:0] a2_re
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,input signed [31:0] b2_re
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,input signed [31:0] a3_re
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,input signed [31:0] b3_re
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,input signed [31:0] a4_re
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,input signed [31:0] b4_re
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,input signed [31:0] a5_re
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,input signed [31:0] b5_re
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,output reg signed [31:0] a_re0
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,output reg signed [31:0] b_re0
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,output reg signed [31:0] ab_re0
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,output reg signed [31:0] abb_re0
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,output reg signed [31:0] ab_pow3_re0
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,output reg signed [31:0] ab_pow4_re0
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,output reg signed [31:0] ab_pow5_re0
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,output reg signed [31:0] ab_pow6_re0
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,output reg signed [31:0] ab_pow7_re0
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,output reg signed [31:0] b_pow8_re0
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,output reg signed [31:0] a_re1
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,output reg signed [31:0] b_re1
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,output reg signed [31:0] ab_re1
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,output reg signed [31:0] abb_re1
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,output reg signed [31:0] ab_pow3_re1
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,output reg signed [31:0] ab_pow4_re1
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,output reg signed [31:0] ab_pow5_re1
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,output reg signed [31:0] ab_pow6_re1
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,output reg signed [31:0] ab_pow7_re1
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,output reg signed [31:0] b_pow8_re1
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,output reg signed [31:0] a_re2
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,output reg signed [31:0] b_re2
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,output reg signed [31:0] ab_re2
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,output reg signed [31:0] abb_re2
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,output reg signed [31:0] ab_pow3_re2
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,output reg signed [31:0] ab_pow4_re2
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,output reg signed [31:0] ab_pow5_re2
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,output reg signed [31:0] ab_pow6_re2
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,output reg signed [31:0] ab_pow7_re2
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,output reg signed [31:0] b_pow8_re2
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,output reg signed [31:0] a_re3
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,output reg signed [31:0] b_re3
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,output reg signed [31:0] ab_re3
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,output reg signed [31:0] abb_re3
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,output reg signed [31:0] ab_pow3_re3
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,output reg signed [31:0] ab_pow4_re3
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,output reg signed [31:0] ab_pow5_re3
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,output reg signed [31:0] ab_pow6_re3
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,output reg signed [31:0] ab_pow7_re3
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,output reg signed [31:0] b_pow8_re3
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,output reg signed [31:0] a_re4
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,output reg signed [31:0] b_re4
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,output reg signed [31:0] ab_re4
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,output reg signed [31:0] abb_re4
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,output reg signed [31:0] ab_pow3_re4
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,output reg signed [31:0] ab_pow4_re4
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,output reg signed [31:0] ab_pow5_re4
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,output reg signed [31:0] ab_pow6_re4
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,output reg signed [31:0] ab_pow7_re4
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,output reg signed [31:0] b_pow8_re4
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,output reg signed [31:0] a_re5
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,output reg signed [31:0] b_re5
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,output reg signed [31:0] ab_re5
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,output reg signed [31:0] abb_re5
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,output reg signed [31:0] ab_pow3_re5
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,output reg signed [31:0] ab_pow4_re5
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,output reg signed [31:0] ab_pow5_re5
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,output reg signed [31:0] ab_pow6_re5
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,output reg signed [31:0] ab_pow7_re5
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,output reg signed [31:0] b_pow8_re5
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);
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reg vldi_or_r1;
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wire vldi_or = | vldi;
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sirv_gnrl_dffr #(1) dff_vldi_or_1(vldi_or, vldi_or_r1 ,clk,rstn);
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reg signed [data_in_width-1:0] a_re_r1;
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reg signed [data_in_width-1:0] b_re_r1;
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always @(posedge clk or negedge rstn) begin
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if(rstn == 1'b0) begin
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a_re_r1 <= 'h0;
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b_re_r1 <= 'h0;
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end
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else if(|vldi) begin
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case(1'b1)
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vldi[0]: begin
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a_re_r1 <= a0_re;
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b_re_r1 <= b0_re;
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end
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vldi[1]: begin
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a_re_r1 <= a1_re;
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b_re_r1 <= b1_re;
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end
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vldi[2]: begin
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a_re_r1 <= a2_re;
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b_re_r1 <= b2_re;
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end
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vldi[3]: begin
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a_re_r1 <= a3_re;
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b_re_r1 <= b3_re;
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end
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vldi[4]: begin
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a_re_r1 <= a4_re;
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b_re_r1 <= b4_re;
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end
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vldi[5]: begin
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a_re_r1 <= a5_re;
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b_re_r1 <= b5_re;
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end
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// default: begin
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// a_re_r1 <= a_re[0];
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// b_re_r1 <= b_re[0];
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// end
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endcase
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end
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end
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reg en;
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reg en_r1;
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sirv_gnrl_dffr #(1) dff_en_1(en, en_r1 ,clk,rstn);
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reg [3:0] cnt0;
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wire add_cnt0;
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wire end_cnt0;
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always @(posedge clk or negedge rstn)begin
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if(!rstn)begin
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cnt0 <= 0;
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end
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else if(add_cnt0)begin
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if(end_cnt0)
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cnt0 <= 0;
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else
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cnt0 <= cnt0 + 1;
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end
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end
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assign add_cnt0 = en;
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assign end_cnt0 = add_cnt0 && cnt0== 8-1;
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wire en_l;
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wire en_h;
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always @(posedge clk or negedge rstn)begin
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if(rstn==1'b0)begin
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en <= 0;
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end
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else if(en_h)begin
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en <= 1;
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end
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else if(en_l)begin
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en <= 0;
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end
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end
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assign en_h = vldi_or == 1 && vldi_or_r1 == 0 && cnt0 == 0;
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assign en_l = end_cnt0;
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reg signed [data_in_width-1:0] bin_re;
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wire signed [data_in_width-1:0] bout_re;
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always @(*)begin
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if(en_r1) begin
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bin_re <= bout_re;
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end
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else begin
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bin_re <= 32'd2147483647;
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end
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end
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mult_real
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#(
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.A_width(data_in_width)
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,.C_width(coef_width)
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,.o_width(data_in_width)
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)
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inst_c1 (
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.din (bin_re ),
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.coef (b_re_r1 ),
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.dout (bout_re )
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);
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wire signed [data_in_width-1:0] abo_re;
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mult_real
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#(
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.A_width(data_in_width)
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,.C_width(coef_width)
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,.o_width(data_in_width)
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)
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inst_c2 (
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.din (bin_re ),
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.coef (a_re_r1 ),
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.dout (abo_re )
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);
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reg signed [coef_width-1 :0] ao_re_r1 ;
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reg signed [coef_width-1 :0] ab_re_r1 ;
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reg signed [coef_width-1 :0] abb_re_r1 ;
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reg signed [coef_width-1 :0] ab_pow3_re_r1 ;
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reg signed [coef_width-1 :0] ab_pow4_re_r1 ;
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reg signed [coef_width-1 :0] ab_pow5_re_r1 ;
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reg signed [coef_width-1 :0] ab_pow6_re_r1 ;
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reg signed [coef_width-1 :0] ab_pow7_re_r1 ;
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reg signed [coef_width-1 :0] bo_re_r1 ;
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reg signed [coef_width-1 :0] b_pow8_re_r1 ;
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always @(posedge clk or negedge rstn)begin
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if(!rstn)begin
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ao_re_r1 <= 0;
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ab_re_r1 <= 0;
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abb_re_r1 <= 0;
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ab_pow3_re_r1 <= 0;
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ab_pow4_re_r1 <= 0;
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ab_pow5_re_r1 <= 0;
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ab_pow6_re_r1 <= 0;
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ab_pow7_re_r1 <= 0;
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bo_re_r1 <= 0;
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b_pow8_re_r1 <= 0;
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end
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else if(add_cnt0 && cnt0 == 1 && en_r1)begin
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ao_re_r1 <= abo_re;
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bo_re_r1 <= bin_re;
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end
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else if(add_cnt0 && cnt0 == 2 && en_r1)begin
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ab_re_r1 <= abo_re;
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end
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else if(add_cnt0 && cnt0 == 3 && en_r1)begin
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abb_re_r1 <= abo_re;
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end
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else if(add_cnt0 && cnt0 == 4 && en_r1)begin
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ab_pow3_re_r1 <= abo_re;
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end
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else if(add_cnt0 && cnt0 == 5 && en_r1)begin
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ab_pow4_re_r1 <= abo_re;
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end
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else if(add_cnt0 && cnt0 == 6 && en_r1)begin
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ab_pow5_re_r1 <= abo_re;
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end
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else if(add_cnt0 && cnt0 == 7 && en_r1)begin
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ab_pow6_re_r1 <= abo_re;
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end
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else if(cnt0 == 0 && en_r1)begin
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ab_pow7_re_r1 <= abo_re;
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b_pow8_re_r1 <= bin_re;
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end
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// else begin
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// end
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end
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reg [5:0] vldi_r1;
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reg [5:0] vldi_r2;
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reg [5:0] vldi_r3;
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reg [5:0] vldi_r4;
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reg [5:0] vldi_r5;
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reg [5:0] vldi_r6;
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reg [5:0] vldi_r7;
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reg [5:0] vldi_r8;
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reg [5:0] vldi_r9;
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reg [5:0] vldi_r10;
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//syncer #(6, 10) sync_vldo_syncer (clk, rstn, vldi, vldi_r10);
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sirv_gnrl_dffr #(6) dff_vldi_1(vldi,vldi_r1,clk,rstn);
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sirv_gnrl_dffr #(6) dff_vldi_2(vldi_r1, vldi_r2 ,clk,rstn);
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sirv_gnrl_dffr #(6) dff_vldi_3(vldi_r2, vldi_r3 ,clk,rstn);
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sirv_gnrl_dffr #(6) dff_vldi_4(vldi_r3, vldi_r4 ,clk,rstn);
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sirv_gnrl_dffr #(6) dff_vldi_5(vldi_r4, vldi_r5 ,clk,rstn);
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sirv_gnrl_dffr #(6) dff_vldi_6(vldi_r5, vldi_r6 ,clk,rstn);
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sirv_gnrl_dffr #(6) dff_vldi_7(vldi_r6, vldi_r7 ,clk,rstn);
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sirv_gnrl_dffr #(6) dff_vldi_8(vldi_r7, vldi_r8 ,clk,rstn);
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sirv_gnrl_dffr #(6) dff_vldi_9(vldi_r8, vldi_r9 ,clk,rstn);
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sirv_gnrl_dffr #(6) dff_vldi_10(vldi_r9, vldi_r10,clk,rstn);
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always @(posedge clk or negedge rstn) begin
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if(!rstn) begin
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a_re0 <= 0;
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b_re0 <= 0;
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ab_re0 <= 0;
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abb_re0 <= 0;
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ab_pow3_re0 <= 0;
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ab_pow4_re0 <= 0;
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ab_pow5_re0 <= 0;
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ab_pow6_re0 <= 0;
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ab_pow7_re0 <= 0;
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b_pow8_re0 <= 0;
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a_re1 <= 0;
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b_re1 <= 0;
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ab_re1 <= 0;
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abb_re1 <= 0;
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ab_pow3_re1 <= 0;
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ab_pow4_re1 <= 0;
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ab_pow5_re1 <= 0;
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ab_pow6_re1 <= 0;
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ab_pow7_re1 <= 0;
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b_pow8_re1 <= 0;
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a_re2 <= 0;
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b_re2 <= 0;
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ab_re2 <= 0;
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abb_re2 <= 0;
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ab_pow3_re2 <= 0;
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ab_pow4_re2 <= 0;
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ab_pow5_re2 <= 0;
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ab_pow6_re2 <= 0;
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ab_pow7_re2 <= 0;
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b_pow8_re2 <= 0;
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a_re3 <= 0;
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b_re3 <= 0;
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ab_re3 <= 0;
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abb_re3 <= 0;
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ab_pow3_re3 <= 0;
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ab_pow4_re3 <= 0;
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ab_pow5_re3 <= 0;
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ab_pow6_re3 <= 0;
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ab_pow7_re3 <= 0;
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b_pow8_re3 <= 0;
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a_re4 <= 0;
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b_re4 <= 0;
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ab_re4 <= 0;
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abb_re4 <= 0;
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ab_pow3_re4 <= 0;
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ab_pow4_re4 <= 0;
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ab_pow5_re4 <= 0;
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ab_pow6_re4 <= 0;
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ab_pow7_re4 <= 0;
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b_pow8_re4 <= 0;
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a_re5 <= 0;
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b_re5 <= 0;
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ab_re5 <= 0;
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abb_re5 <= 0;
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ab_pow3_re5 <= 0;
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ab_pow4_re5 <= 0;
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ab_pow5_re5 <= 0;
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ab_pow6_re5 <= 0;
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ab_pow7_re5 <= 0;
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b_pow8_re5 <= 0;
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end
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else if(|vldi_r10) begin
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case(1'b1)
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vldi_r10[0]: begin
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a_re0 <= ao_re_r1 ;
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b_re0 <= bo_re_r1 ;
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ab_re0 <= ab_re_r1 ;
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abb_re0 <= abb_re_r1 ;
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ab_pow3_re0 <= ab_pow3_re_r1;
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ab_pow4_re0 <= ab_pow4_re_r1;
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ab_pow5_re0 <= ab_pow5_re_r1;
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ab_pow6_re0 <= ab_pow6_re_r1;
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ab_pow7_re0 <= ab_pow7_re_r1;
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b_pow8_re0 <= b_pow8_re_r1 ;
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end
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vldi_r10[1]: begin
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a_re1 <= ao_re_r1 ;
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b_re1 <= bo_re_r1 ;
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ab_re1 <= ab_re_r1 ;
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abb_re1 <= abb_re_r1 ;
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ab_pow3_re1 <= ab_pow3_re_r1;
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ab_pow4_re1 <= ab_pow4_re_r1;
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ab_pow5_re1 <= ab_pow5_re_r1;
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ab_pow6_re1 <= ab_pow6_re_r1;
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ab_pow7_re1 <= ab_pow7_re_r1;
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b_pow8_re1 <= b_pow8_re_r1 ;
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end
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vldi_r10[2]: begin
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a_re2 <= ao_re_r1 ;
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b_re2 <= bo_re_r1 ;
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ab_re2 <= ab_re_r1 ;
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abb_re2 <= abb_re_r1 ;
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ab_pow3_re2 <= ab_pow3_re_r1;
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ab_pow4_re2 <= ab_pow4_re_r1;
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ab_pow5_re2 <= ab_pow5_re_r1;
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ab_pow6_re2 <= ab_pow6_re_r1;
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ab_pow7_re2 <= ab_pow7_re_r1;
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b_pow8_re2 <= b_pow8_re_r1 ;
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end
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vldi_r10[3]: begin
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a_re3 <= ao_re_r1 ;
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b_re3 <= bo_re_r1 ;
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ab_re3 <= ab_re_r1 ;
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abb_re3 <= abb_re_r1 ;
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ab_pow3_re3 <= ab_pow3_re_r1;
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ab_pow4_re3 <= ab_pow4_re_r1;
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ab_pow5_re3 <= ab_pow5_re_r1;
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ab_pow6_re3 <= ab_pow6_re_r1;
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ab_pow7_re3 <= ab_pow7_re_r1;
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b_pow8_re3 <= b_pow8_re_r1 ;
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end
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vldi_r10[4]: begin
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a_re4 <= ao_re_r1 ;
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b_re4 <= bo_re_r1 ;
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ab_re4 <= ab_re_r1 ;
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abb_re4 <= abb_re_r1 ;
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ab_pow3_re4 <= ab_pow3_re_r1;
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ab_pow4_re4 <= ab_pow4_re_r1;
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ab_pow5_re4 <= ab_pow5_re_r1;
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ab_pow6_re4 <= ab_pow6_re_r1;
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ab_pow7_re4 <= ab_pow7_re_r1;
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b_pow8_re4 <= b_pow8_re_r1 ;
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end
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vldi_r10[5]: begin
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a_re5 <= ao_re_r1 ;
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b_re5 <= bo_re_r1 ;
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ab_re5 <= ab_re_r1 ;
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abb_re5 <= abb_re_r1 ;
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ab_pow3_re5 <= ab_pow3_re_r1;
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ab_pow4_re5 <= ab_pow4_re_r1;
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ab_pow5_re5 <= ab_pow5_re_r1;
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ab_pow6_re5 <= ab_pow6_re_r1;
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ab_pow7_re5 <= ab_pow7_re_r1;
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b_pow8_re5 <= b_pow8_re_r1 ;
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end
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// default: begin
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// ao_re[0] <= 'h0;
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// ab_re[0] <= 'h0;
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// abb_re[0] <= 'h0;
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// ab_pow3_re[0] <= 'h0;
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// ab_pow4_re[0] <= 'h0;
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// ab_pow5_re[0] <= 'h0;
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// ab_pow6_re[0] <= 'h0;
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// ab_pow7_re[0] <= 'h0;
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// b_pow8_re[0] <= 'h0;
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// end
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endcase
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end
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end
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endmodule
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