234 lines
6.7 KiB
Verilog
234 lines
6.7 KiB
Verilog
//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : Z_dsp_en_Test.v
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// Department :
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// Author : thfu
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.1 2024-11-04 thfu Test Enable signal using clk divided by 2
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module z_dsp_en_Test
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(
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clk,
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rstn,
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dac_mode_sel, //2'b00:NRZ mode;2'b01:Double data mode;
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//2'b10:Double Double data mode;2'b11:reserve;
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tc_bypass,
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intp_mode, //2'b00:x1;2'b01:x2,'b10:x4;other:reserve;
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din_re,
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din_im,
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a0_re, //a0's real part
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a0_im, //a0's image part
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b0_re,
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b0_im,
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a1_re,
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a1_im,
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b1_re,
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b1_im,
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a2_re,
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a2_im,
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b2_re,
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b2_im,
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a3_re,
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a3_im,
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b3_re,
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b3_im,
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a4_re,
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a4_im,
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b4_re,
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b4_im,
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a5_re,
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a5_im,
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b5_re,
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b5_im,
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dout0,
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dout1,
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dout2,
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dout3,
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dout4,
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dout5,
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dout6,
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dout7,
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vldo
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);
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input rstn;
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input clk;
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input tc_bypass;
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input [1:0] intp_mode;
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input [1:0] dac_mode_sel;
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input signed [15:0] din_re;
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input signed [15:0] din_im;
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input signed [36:0] a0_re;
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input signed [36:0] a0_im;
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input signed [20:0] b0_re;
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input signed [20:0] b0_im;
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input signed [36:0] a1_re;
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input signed [36:0] a1_im;
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input signed [20:0] b1_re;
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input signed [20:0] b1_im;
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input signed [36:0] a2_re;
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input signed [36:0] a2_im;
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input signed [20:0] b2_re;
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input signed [20:0] b2_im;
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input signed [36:0] a3_re;
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input signed [36:0] a3_im;
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input signed [20:0] b3_re;
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input signed [20:0] b3_im;
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input signed [36:0] a4_re;
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input signed [36:0] a4_im;
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input signed [20:0] b4_re;
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input signed [20:0] b4_im;
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input signed [36:0] a5_re;
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input signed [36:0] a5_im;
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input signed [20:0] b5_re;
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input signed [20:0] b5_im;
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output signed [15:0] dout0;
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output signed [15:0] dout1;
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output signed [15:0] dout2;
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output signed [15:0] dout3;
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output signed [15:0] dout4;
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output signed [15:0] dout5;
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output signed [15:0] dout6;
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output signed [15:0] dout7;
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output vldo;
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wire signed [15:0] IIR_out;
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reg en;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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en <= 0;
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else
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en <= ~en;
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reg [10:0] vldo_r;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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begin
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vldo_r <= 9'b0;
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end
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else
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begin
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vldo_r <= {vldo_r[10:0], en};
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end
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assign vldo = vldo_r[10];
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TailCorr_top inst_TailCorr_top
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(
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.tc_bypass (tc_bypass ),
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.din_re (din_re ),
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.din_im (din_im ),
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.a0_re (a0_re ),
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.a0_im (a0_im ),
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.b0_re (b0_re ),
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.b0_im (b0_im ),
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.a1_re (a1_re ),
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.a1_im (a1_im ),
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.b1_re (b1_re ),
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.b1_im (b1_im ),
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.a2_re (a2_re ),
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.a2_im (a2_im ),
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.b2_re (b2_re ),
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.b2_im (b2_im ),
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.a3_re (a3_re ),
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.a3_im (a3_im ),
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.b3_re (b3_re ),
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.b3_im (b3_im ),
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.a4_re (a4_re ),
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.a4_im (a4_im ),
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.b4_re (b4_re ),
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.b4_im (b4_im ),
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.a5_re (a5_re ),
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.a5_im (a5_im ),
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.b5_re (b5_re ),
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.b5_im (b5_im ),
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.dout (IIR_out )
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);
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wire signed [15:0] dout_0;
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wire signed [15:0] dout_1;
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wire signed [15:0] dout_2;
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wire signed [15:0] dout_3;
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wire signed [15:0] dout_4;
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wire signed [15:0] dout_5;
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wire signed [15:0] dout_6;
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wire signed [15:0] dout_7;
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MeanIntp_8 inst_MeanIntp_8
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(
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.intp_mode (intp_mode ),
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.din (IIR_out ),
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.dout_0 (dout_0 ),
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.dout_1 (dout_1 ),
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.dout_2 (dout_2 ),
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.dout_3 (dout_3 ),
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.dout_4 (dout_4 ),
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.dout_5 (dout_5 ),
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.dout_6 (dout_6 ),
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.dout_7 (dout_7 )
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);
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lsdacif inst_lsdacif
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(
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.clk (clk ),
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.rstn (rstn ),
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.dac_mode_sel (dac_mode_sel ),
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.intp_mode (intp_mode ),
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.din0 (dout_0 ),
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.din1 (dout_1 ),
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.din2 (dout_2 ),
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.din3 (dout_3 ),
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.din4 (dout_4 ),
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.din5 (dout_5 ),
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.din6 (dout_6 ),
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.din7 (dout_7 ),
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.dout0 (dout0 ),
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.dout1 (dout1 ),
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.dout2 (dout2 ),
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.dout3 (dout3 ),
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.dout4 (dout4 ),
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.dout5 (dout5 ),
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.dout6 (dout6 ),
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.dout7 (dout7 )
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);
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endmodule
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