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拖尾矫正
8 Commits 4 Branches 0 Tags 22 MiB
Verilog 80.6%
SystemVerilog 13.1%
MATLAB 3.5%
Coq 1.2%
Makefile 1.1%
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thfu da3157a7d8 Modify enable signal as clk divided by 2 2024-11-04 19:03:02 +08:00
rtl Modify enable signal as clk divided by 2 2024-11-04 19:03:02 +08:00
script_m modify relevant .v file and .m file to verify the accuracy of rtl code 2024-10-17 17:29:11 +08:00
sim modify relevant .v file and .m file to verify the accuracy of rtl code 2024-10-17 17:29:11 +08:00
tb Modify enable signal as clk divided by 2 2024-11-04 19:03:02 +08:00