65 lines
1.0 KiB
Verilog
Executable File
65 lines
1.0 KiB
Verilog
Executable File
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module PIPE3_ACC_48BIT(
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clk,
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rstn,
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in,
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clr,
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ptw,
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s_i_1,
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s_i_2,
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s_i_3,
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s_o_1,
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s_o_2,
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s_o_3,
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out
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);
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//---
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input clk;
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input rstn;
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input [47:0] in;
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input clr;
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input [15:0] ptw;
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input [15:0] s_i_1;
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input [15:0] s_i_2;
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input [15:0] s_i_3;
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output [15:0] s_o_1;
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output [15:0] s_o_2;
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output [15:0] s_o_3;
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output [18:0] out;
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//----------------------------------------------------------------------------------------------------
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reg [47:0] acc;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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acc<=48'h0;
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else if(clr)
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acc<=48'h0;
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else
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acc<={s_i_1,s_i_2,s_i_3}+in;
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//----------------------------------------------------------------------------------------------------
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wire [15:0] s1;
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wire [15:0] s2;
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wire [15:0] s3;
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assign s_o_1 = acc[47:32];
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assign s_o_2 = acc[31:16];
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assign s_o_3 = acc[15:0];
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wire[18:0] pha_w;
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assign pha_w=acc[47:29];
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reg[18:0] pha_r;
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always@(posedge clk)
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pha_r<=pha_w+{ptw,3'b0};
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assign out=pha_r;
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//END
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endmodule
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