52 lines
1.3 KiB
Verilog
Executable File
52 lines
1.3 KiB
Verilog
Executable File
module NCO(
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clk,
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rstn,
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phase_manual_clr,
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phase_auto_clr,
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fcw,
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pha,
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cos,
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sin
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);
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input clk;
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input rstn;
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input phase_manual_clr;
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input phase_auto_clr;
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input [47:0] fcw;
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input [15:0] pha;
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output [15:0] cos;
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output [15:0] sin;
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wire clr_acc;
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wire clr_fix;
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assign clr_acc = phase_auto_clr | phase_manual_clr;
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assign clr_fix = phase_manual_clr;
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wire [15:0] s1_i_o;
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wire [15:0] s2_i_o;
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wire [15:0] s3_i_o;
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P_NCO inst_p_nco(
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.clk (clk ),
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.rstn (rstn ),
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.clr (clr_fix ),
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.clr_acc (clr_acc ),
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.pha (pha ),
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.s1 (s1_i_o ),
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.s2 (s2_i_o ),
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.s3 (s3_i_o ),
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.s1_o (s1_i_o ),
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.s2_o (s2_i_o ),
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.s3_o (s3_i_o ),
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.fcw (fcw ),
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.cos (cos ),
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.sin (sin )
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);
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endmodule
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