84 lines
1.6 KiB
Verilog
Executable File
84 lines
1.6 KiB
Verilog
Executable File
module PH2AMP(
|
|
clk ,
|
|
rstn ,
|
|
pha_map ,
|
|
sin_o ,
|
|
cos_o
|
|
);
|
|
input clk;
|
|
input rstn;
|
|
input [18:0] pha_map;
|
|
|
|
output [15:0] sin_o;
|
|
output [15:0] cos_o;
|
|
|
|
//wire [2:0] pha_indx_msb_s;
|
|
wire [14:0] sin_w;
|
|
SIN_OP inst_sin_op(
|
|
.clk(clk),
|
|
.rstn(rstn),
|
|
.pha_map(pha_map),
|
|
// .pha_indx_msb(pha_indx_msb_s),
|
|
.sin_op_o(sin_w)
|
|
);
|
|
wire [2:0] pha_indx_msb_c;
|
|
wire [14:0] cos_w;
|
|
COS_OP inst_cos_op(
|
|
.clk(clk) ,
|
|
.rstn(rstn) ,
|
|
.pha_map(pha_map) ,
|
|
.pha_indx_msb(pha_indx_msb_c),
|
|
.cos_op_o(cos_w)
|
|
);
|
|
wire[15:0] cos_w_1;
|
|
wire[15:0] sin_w_1;
|
|
wire[15:0] cos_w_0;
|
|
wire[15:0] sin_w_0;//0:-,1:+
|
|
|
|
assign cos_w_1={1'b0,cos_w};
|
|
assign sin_w_1={1'b0,sin_w};
|
|
assign cos_w_0=(cos_w_1==16'd0)?16'd0:~cos_w_1+16'd1;
|
|
assign sin_w_0=(sin_w_1==16'd0)?16'd0:~sin_w_1+16'd1;
|
|
|
|
reg[15:0] cos_tmp;
|
|
reg[15:0] sin_tmp;
|
|
always@(posedge clk)
|
|
case(pha_indx_msb_c)//synopsys parallel_case
|
|
3'b000:begin
|
|
cos_tmp<=cos_w_1;
|
|
sin_tmp<=sin_w_1;
|
|
end
|
|
3'b001:begin
|
|
cos_tmp<=sin_w_1;
|
|
sin_tmp<=cos_w_1;
|
|
end
|
|
3'b010:begin
|
|
cos_tmp<=sin_w_0;
|
|
sin_tmp<=cos_w_1;
|
|
end
|
|
3'b011:begin
|
|
cos_tmp<=cos_w_0;
|
|
sin_tmp<=sin_w_1;
|
|
end
|
|
3'b100:begin
|
|
cos_tmp<=cos_w_0;
|
|
sin_tmp<=sin_w_0;
|
|
end
|
|
3'b101:begin
|
|
cos_tmp<=sin_w_0;
|
|
sin_tmp<=cos_w_0;
|
|
end
|
|
3'b110:begin
|
|
cos_tmp<=sin_w_1;
|
|
sin_tmp<=cos_w_0;
|
|
end
|
|
3'b111:begin
|
|
cos_tmp<=cos_w_1;
|
|
sin_tmp<=sin_w_0;
|
|
end
|
|
endcase
|
|
|
|
assign sin_o=sin_tmp;
|
|
assign cos_o=cos_tmp;
|
|
endmodule
|