57 lines
1.5 KiB
Verilog
57 lines
1.5 KiB
Verilog
module trunc #(
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parameter integer diw = 8
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//,parameter integer dow = msb - (lsb -1)
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,parameter integer msb = 7
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,parameter integer lsb = 1
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,parameter integer half_precision = 0
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)
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(
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input clk
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,input rstn
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,input en
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,input signed [diw - 1 :0] din
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,output signed [msb - lsb:0] dout
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);
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reg signed [msb - lsb : 0] d_tmp;
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generate
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if(lsb!=0 && half_precision != 0) begin
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always @(posedge clk or negedge rstn) begin
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if (!rstn) begin
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d_tmp <= 'h0;
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end
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else if(en) begin
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if(din[diw-1 : msb] != {(diw-msb){din[diw-1]}})
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d_tmp <= {{din[diw-1]}, {(msb-lsb){!din[diw-1]}}};
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else
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d_tmp <= din[msb:lsb] + {{(msb-lsb){1'b0}},din[lsb-1]};
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end
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else begin
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d_tmp <= d_tmp;
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end
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end
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end
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else begin
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always @(posedge clk or negedge rstn) begin
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if (!rstn) begin
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d_tmp <= 'h0;
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end
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else if(en) begin
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if(din[diw-1 : msb] != {(diw-msb){din[diw-1]}})
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d_tmp <= {{din[diw-1]}, {(msb-lsb){!din[diw-1]}}};
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else
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d_tmp <= din[msb:lsb];
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end
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else begin
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d_tmp <= d_tmp;
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end
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end
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end
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endgenerate
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assign dout = d_tmp;
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endmodule
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