131 lines
2.3 KiB
Verilog
131 lines
2.3 KiB
Verilog
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`timescale 1ns/1ps
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module TB();
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initial
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begin
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$fsdbDumpfile("TB.fsdb");
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$fsdbDumpvars(0, TB);
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end
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reg clk;
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reg rst_n;
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reg [15:0] din;
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reg enable;
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reg [21:0] cnt;
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wire [15:0] dout0;
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wire [15:0] dout1;
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s2p_2 uut (
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.clk (clk),
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.rst_n (rst_n),
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.din (din),
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.en (enable),
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.dout0 (dout0),
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.dout1 (dout1)
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);
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reg[15:0] din_r1;
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always @(posedge clk or negedge rst_n)begin
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if(rst_n==1'b0)begin
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din_r1 <= 0;
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end
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else begin
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din_r1 <= din;
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end
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end
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wire signed [15:0] diff;
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assign diff = din - din_r1;
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reg[15:0] dout1_r1;
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reg[15:0] dout1_r2;
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always @(posedge clk or negedge rst_n)begin
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if(rst_n==1'b0)begin
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dout1_r1 <= 0;
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dout1_r2 <= 0;
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end
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else begin
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dout1_r1 <= dout1;
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dout1_r2 <= dout1_r1;
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end
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end
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wire signed [15:0] diff12;
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wire signed [15:0] diff23;
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assign diff12 = dout0 - dout1_r2;
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assign diff23 = dout1 - dout0;
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initial begin
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rst_n = 0;
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enable = 0;
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clk = 1'b0;
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din = 16'h0000;
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#20;
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rst_n = 1;
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#10;
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end
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always #5 clk = ~clk;
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always @(posedge clk or negedge rst_n) begin
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if (rst_n == 1'b0) begin
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cnt <= 22'd0;
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end else begin
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cnt <= cnt + 22'd1;
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end
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end
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reg [15:0] enable_cnt;
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always @(posedge clk or negedge rst_n) begin
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if (rst_n == 1'b0) begin
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enable <= 0;
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din <= 16'd0;
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enable_cnt <= 0;
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end else begin
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if (cnt < 1000) begin
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if (enable_cnt == 0) begin
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if ($urandom % 2 == 0) begin
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enable <= 1;
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enable_cnt <= $urandom % 10 + 5;
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din <= $urandom;
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end else begin
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enable <= 0;
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din <= 16'd0;
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end
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end else begin
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enable <= 1;
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enable_cnt <= enable_cnt - 1;
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din <= $urandom;
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end
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end else begin
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enable <= 0;
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din <= 16'd0;
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end
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end
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end
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initial begin
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wait(cnt[11] == 1);
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$finish;
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end
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endmodule
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