100 lines
3.0 KiB
Verilog
100 lines
3.0 KiB
Verilog
////////////////////////////////////////////////////////////////////////////////
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//
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// This confidential and proprietary software may be used only
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// as authorized by a licensing agreement from Synopsys Inc.
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// In the event of publication, the following notice is applicable:
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//
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// (C) COPYRIGHT 1994 - 2018 SYNOPSYS INC.
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// ALL RIGHTS RESERVED
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//
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// The entire notice above must be reproduced on all authorized
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// copies.
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//
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// AUTHOR: KB WSFDB June 30, 1994
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//
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// VERSION: Simulation Architecture
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//
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// DesignWare_version: 714fe7a9
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// DesignWare_release: O-2018.06-DWBB_201806.3
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//
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////////////////////////////////////////////////////////////////////////////////
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//-----------------------------------------------------------------------------------
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//
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// ABSTRACT: Multiplier
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// A_width-Bits * B_width-Bits => A_width+B_width Bits
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// Operands A and B can be either both signed (two's complement) or
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// both unsigned numbers. TC determines the coding of the input operands.
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// ie. TC = '1' => signed multiplication
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// TC = '0' => unsigned multiplication
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//
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// FIXED: by replacement with A tested working version
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// that not only doesn't multiplies right it does it
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// two times faster!
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// RPH 07/17/2002
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// Rewrote to comply with the new guidelines
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//------------------------------------------------------------------------------
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module DW02_mult(A,B,TC,PRODUCT);
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parameter integer A_width = 8;
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parameter integer B_width = 8;
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input [A_width-1:0] A;
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input [B_width-1:0] B;
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input TC;
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output [A_width+B_width-1:0] PRODUCT;
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wire [A_width+B_width-1:0] PRODUCT;
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wire [A_width-1:0] temp_a;
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wire [B_width-1:0] temp_b;
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wire [A_width+B_width-2:0] long_temp1,long_temp2;
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//-------------------------------------------------------------------------
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// Parameter legality check
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//-------------------------------------------------------------------------
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initial begin : parameter_check
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integer param_err_flg;
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param_err_flg = 0;
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if (A_width < 1) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter A_width (lower bound: 1)",
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A_width );
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end
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if (B_width < 1) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter B_width (lower bound: 1)",
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B_width );
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end
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if ( param_err_flg == 1) begin
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$display(
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"%m :\n Simulation aborted due to invalid parameter value(s)");
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$finish;
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end
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end // parameter_check
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assign temp_a = (A[A_width-1])? (~A + 1'b1) : A;
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assign temp_b = (B[B_width-1])? (~B + 1'b1) : B;
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assign long_temp1 = temp_a * temp_b;
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assign long_temp2 = ~(long_temp1 - 1'b1);
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assign PRODUCT = ((^(A ^ A) !== 1'b0) || (^(B ^ B) !== 1'b0) || (^(TC ^ TC) !== 1'b0) ) ? {A_width+B_width{1'bX}} :
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(TC)? (((A[A_width-1] ^ B[B_width-1]) && (|long_temp1))?
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{1'b1,long_temp2} : {1'b0,long_temp1})
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: A * B;
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endmodule
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