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拖尾矫正
24 Commits 4 Branches 0 Tags 22 MiB
Verilog 80.6%
SystemVerilog 13.1%
MATLAB 3.5%
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thfu c00527b128 v04-add valid output port and convert from 8 to 4 on FPGA 2024-11-21 10:53:28 +08:00
edfFile v04-add valid output port and convert from 8 to 4 on FPGA 2024-11-21 10:53:28 +08:00
rtl Modify the directory structure 2th 2024-11-20 20:24:08 +08:00
script_m v04-din+IIR_out to compare with verdi 2024-11-20 20:27:50 +08:00
sim v04-enable of clk_div2 2024-11-12 17:35:22 +08:00
tb v04-add valid output port and convert from 8 to 4 2024-11-14 20:35:56 +08:00