62 lines
1001 B
Verilog
62 lines
1001 B
Verilog
module TB();
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initial
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begin
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$fsdbDumpfile("TB.fsdb");
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$fsdbDumpvars(0, TB);
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end
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reg clk;
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reg rstn;
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reg [15:0] din_in;
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reg [21:0] cnt;
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initial begin
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#0;
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rstn = 1'b0;
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clk = 1'b0;
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din_in = 1'b0;
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#3400;
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rstn = 1'b1;
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din_in = 1'b1;
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#6400;
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rstn = 1'b1;
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din_in = 1'b0;
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end
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always #200 clk = ~clk;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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cnt <= 22'd0;
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else
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cnt <= cnt + 22'd1;
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initial begin
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wait(cnt[16]==1'b1)
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$finish(0);
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end
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reg [47:0] fcw;
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diff inst_diff
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(
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.clk (clk ),
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.rstn (rstn ),
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.din (din_in ),
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.dout (dout_p0 )
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);
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endmodule
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