145 lines
2.8 KiB
Verilog
Executable File
145 lines
2.8 KiB
Verilog
Executable File
module SIN_OP(
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clk,
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rstn,
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pha_map,
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// pha_indx_msb,
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sin_op_o
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);
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input clk;
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input rstn;
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input[18:0] pha_map;
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//output [2:0] pha_indx_msb;
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output [14:0] sin_op_o;
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wire [2:0] pha_indx_msb_w;
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assign pha_indx_msb_w=pha_map[18:16];
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wire [15:0] pha_indx_lsb;
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assign pha_indx_lsb=pha_map[15:0];
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wire [15:0] pha_op;
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assign pha_op=pha_indx_msb_w[0]?(~pha_indx_lsb):pha_indx_lsb;
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wire [4:0] indx;
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assign indx=pha_op[15:11];
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wire [10:0] x_w;
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assign x_w=pha_op[10:0];
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wire [17:0] c0;
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wire [11:0] c1;
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wire [4:0] c2;
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COEF_S coef_s_inst1(
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.index(indx) ,
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.C0_S(c0) ,
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.C1_S(c1) ,
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.C2_S(c2)
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);
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reg[17:0] c0_r1;
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reg[17:0] c0_r2;
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reg[17:0] c0_r3;
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reg[17:0] c0_r4;
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reg[17:0] c0_r5;
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reg[17:0] c0_r6;
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always@(posedge clk)
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begin
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c0_r1<=c0;
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c0_r2<=c0_r1;
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c0_r3<=c0_r2;
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c0_r4<=c0_r3;
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c0_r5<=c0_r4;
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c0_r6<=c0_r5;
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end
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reg [11:0] c1_r1;
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reg [11:0] c1_r2;
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reg [11:0] c1_r3;
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always@(posedge clk)
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begin
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c1_r1<=c1;
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c1_r2<=c1_r1;
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c1_r3<=c1_r2;
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end
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reg [4:0] c2_r1;
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always@(posedge clk)
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c2_r1<=c2;
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reg[10:0] x_r1;
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reg[10:0] x_r2;
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reg[10:0] x_r3;
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reg[10:0] x_r4;
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always@(posedge clk)
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begin
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x_r1<=x_w;
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x_r2<=x_r1;
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x_r3<=x_r2;
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x_r4<=x_r3;
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end
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wire [15:0] c2x;
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DW_mult_pipe #(11,5,2,0,1) inst_mult_0(
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.clk (clk ),
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.rst_n (rstn ),
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.en (1'b1 ),
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.a (x_r1 ),
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.b (c2_r1 ),
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.tc (1'b0 ),
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.product (c2x )
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);
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wire [4:0] c2x_w;
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assign c2x_w=c2x[10]?(c2x[15:11]+5'd1):c2x[15:11];
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reg [11:0] c2xc1;
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always@(posedge clk)
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c2xc1<=c1_r2-c2x_w;
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wire [22:0] c2xc1x;
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DW_mult_pipe #(11,12,3,0,1) inst_mult_1(
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.clk (clk ),
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.rst_n (rstn ),
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.en (1'b1 ),
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.a (x_r3 ),
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.b (c2xc1 ),
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.tc (1'b0 ),
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.product (c2xc1x )
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);
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wire [12:0] c2xc1x_w;
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assign c2xc1x_w=c2xc1x[9]?(c2xc1x[22:10]+13'd1):c2xc1x[22:10];
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reg [12:0] c2xc1x_r;
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always@(posedge clk)
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c2xc1x_r<=c2xc1x_w;
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wire[17:0] c2xc1xc0;
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assign c2xc1xc0=c0_r6+c2xc1x_r;
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wire [14:0] c2xc1xc0_w;
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assign c2xc1xc0_w=c2xc1xc0[2]?(c2xc1xc0[17:3]+13'd1):c2xc1xc0[17:3];
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reg [14:0] c2xc1xc0_r;
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always@(posedge clk)
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c2xc1xc0_r<=c2xc1xc0_w;
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assign sin_op_o=c2xc1xc0_r;
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/*
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reg[2:0] pha_indx_msb_r1;
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reg[2:0] pha_indx_msb_r2;
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reg[2:0] pha_indx_msb_r3;
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reg[2:0] pha_indx_msb_r4;
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reg[2:0] pha_indx_msb_r5;
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reg[2:0] pha_indx_msb_r6;
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reg[2:0] pha_indx_msb_r7;
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always@(posedge clk)
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begin
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pha_indx_msb_r1<=pha_indx_msb_w;
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pha_indx_msb_r2<=pha_indx_msb_r1;
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pha_indx_msb_r3<=pha_indx_msb_r2;
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pha_indx_msb_r4<=pha_indx_msb_r3;
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pha_indx_msb_r5<=pha_indx_msb_r4;
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pha_indx_msb_r6<=pha_indx_msb_r5;
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pha_indx_msb_r7<=pha_indx_msb_r6;
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end
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end
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assign pha_indx_msb=pha_indx_msb_r7;
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*/
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endmodule
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