588 lines
32 KiB
Verilog
588 lines
32 KiB
Verilog
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module IIR_top #(
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parameter data_out_width = 18
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,parameter coef_width = 32
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,parameter a0_width = 32
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,parameter b0_width = 29
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,parameter b0_i_width = 29
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,parameter b0_o_width = 19
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,parameter a1_width = 19
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,parameter b1_width = 19
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,parameter b1_i_width = 19
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,parameter b1_o_width = 19
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,parameter a2_width = 21
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,parameter b2_width = 21
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,parameter b2_i_width = 19
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,parameter b2_o_width = 19
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,parameter a3_width = 21
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,parameter b3_width = 21
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,parameter b3_i_width = 19
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,parameter b3_o_width = 19
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,parameter a4_width = 20
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,parameter b4_width = 20
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,parameter b4_i_width = 19
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,parameter b4_o_width = 18
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,parameter a5_width = 21
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,parameter b5_width = 21
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,parameter b5_i_width = 18
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,parameter b5_o_width = 18
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,parameter a6_width = 21
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,parameter b6_width = 21
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,parameter b6_i_width = 18
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,parameter b6_o_width = 18
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,parameter a7_width = 22
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,parameter b7_width = 22
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,parameter b7_i_width = 18
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,parameter b7_o_width = 18
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,parameter a8_width = 23
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,parameter b8_width = 23
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,parameter b8_i_width = 18
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,parameter b8_o_width = 18
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,parameter a9_width = 24
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,parameter b9_width = 24
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,parameter b9_i_width = 18
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,parameter b9_o_width = 18
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,parameter a10_width = 25
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,parameter b10_width = 25
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,parameter b10_i_width = 18
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,parameter b10_o_width = 18
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,parameter a11_width = 26
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,parameter b11_width = 26
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,parameter b11_i_width = 18
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,parameter b11_o_width = 18
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,parameter a12_width = 27
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,parameter b12_width = 27
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,parameter b12_i_width = 18
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,parameter b12_o_width = 18
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,parameter a13_width = 28
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,parameter b13_width = 28
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,parameter b13_i_width = 18
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,parameter b13_o_width = 18
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,parameter a14_width = 29
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,parameter b14_width = 29
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,parameter b14_i_width = 18
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,parameter b14_o_width = 18
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,parameter a15_width = 29
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,parameter b15_width = 29
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,parameter b15_i_width = 18
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,parameter b15_o_width = 18
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)
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(
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input rstn
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,input clk
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,input en
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,input signed [15 :0] IIRin_p0 // x(8n+9)
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,input signed [15 :0] IIRin_p1 // x(8n+10)
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,input signed [15 :0] IIRin_p2 // x(8n+11)
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,input signed [15 :0] IIRin_p3 // x(8n+12)
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,input signed [15 :0] IIRin_p4 // x(8n+13)
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,input signed [15 :0] IIRin_p5 // x(8n+14)
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,input signed [15 :0] IIRin_p6 // x(8n+15)
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,input signed [15 :0] IIRin_p7 // x(8n+16)
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,input signed [15 :0] IIRin_p8 // x(8n+9)
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,input signed [15 :0] IIRin_p9 // x(8n+10)
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,input signed [15 :0] IIRin_pa // x(8n+11)
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,input signed [15 :0] IIRin_pb // x(8n+12)
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,input signed [15 :0] IIRin_pc // x(8n+13)
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,input signed [15 :0] IIRin_pd // x(8n+14)
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,input signed [15 :0] IIRin_pe // x(8n+15)
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,input signed [15 :0] IIRin_pf // x(8n+16)
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,input signed [15 :0] IIRin_p0_r2 // x(8n+9) delay 2M -> x(8n- 7)
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,input signed [15 :0] IIRin_p1_r4 // x(8n+10) delay 4M -> x(8n-22)
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,input signed [15 :0] IIRin_p2_r6 // x(8n+11) delay 6M -> x(8n-37)
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,input signed [15 :0] IIRin_p3_r8 // x(8n+12) delay 8M -> x(8n-52)
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,input signed [15 :0] IIRin_p4_r10 // x(8n+13) delay 10M -> x(8n-67)
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,input signed [15 :0] IIRin_p5_r12 // x(8n+14) delay 12M -> x(8n-82)
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,input signed [15 :0] IIRin_p6_r14 // x(8n+15) delay 14M -> x(8n-97)
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,input signed [15 :0] IIRin_p7_r16 // x(8n+16) delay 16M -> x(8n-112)
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,input signed [15 :0] IIRin_p8_r18 // x(8n+15) delay 18M -> x(8n-127)
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,input signed [15 :0] IIRin_p9_r20 // x(8n+14) delay 20M -> x(8n-142)
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,input signed [15 :0] IIRin_pa_r22 // x(8n+13) delay 22M -> x(8n-157)
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,input signed [15 :0] IIRin_pb_r24 // x(8n+12) delay 24M -> x(8n-172)
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,input signed [15 :0] IIRin_pc_r26 // x(8n+11) delay 26M -> x(8n-187)
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,input signed [15 :0] IIRin_pd_r28 // x(8n+10) delay 28M -> x(8n-202)
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,input signed [15 :0] IIRin_pe_r30 // x(8n+9) delay 30M -> x(8n-217)
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,input signed [31 :0] a_re
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,input signed [31 :0] b_re
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,input signed [31 :0] ab_re
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,input signed [31 :0] abb_re
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,input signed [31 :0] ab_pow3_re
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,input signed [31 :0] ab_pow4_re
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,input signed [31 :0] ab_pow5_re
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,input signed [31 :0] ab_pow6_re
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,input signed [31 :0] ab_pow7_re
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,input signed [31 :0] ab_pow8_re
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,input signed [31 :0] ab_pow9_re
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,input signed [31 :0] ab_powa_re
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,input signed [31 :0] ab_powb_re
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,input signed [31 :0] ab_powc_re
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,input signed [31 :0] ab_powd_re
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,input signed [31 :0] ab_powe_re
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,input signed [31 :0] ab_powf_re
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,input signed [31 :0] b_pow16_re
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,input signed [31 :0] a_im
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,input signed [31 :0] b_im
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,input signed [31 :0] ab_im
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,input signed [31 :0] abb_im
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,input signed [31 :0] ab_pow3_im
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,input signed [31 :0] ab_pow4_im
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,input signed [31 :0] ab_pow5_im
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,input signed [31 :0] ab_pow6_im
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,input signed [31 :0] ab_pow7_im
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,input signed [31 :0] ab_pow8_im
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,input signed [31 :0] ab_pow9_im
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,input signed [31 :0] ab_powa_im
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,input signed [31 :0] ab_powb_im
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,input signed [31 :0] ab_powc_im
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,input signed [31 :0] ab_powd_im
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,input signed [31 :0] ab_powe_im
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,input signed [31 :0] ab_powf_im
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,input signed [31 :0] b_pow16_im
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,output signed [data_out_width-1 :0] IIRout_p0 // y(8n-8)
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,output signed [data_out_width-1 :0] IIRout_p1 // y(8n-23)
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,output signed [data_out_width-1 :0] IIRout_p2 // y(8n-38)
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,output signed [data_out_width-1 :0] IIRout_p3 // y(8n-53)
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,output signed [data_out_width-1 :0] IIRout_p4 // y(8n-68)
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,output signed [data_out_width-1 :0] IIRout_p5 // y(8n-83)
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,output signed [data_out_width-1 :0] IIRout_p6 // y(8n-98)
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,output signed [data_out_width-1 :0] IIRout_p7 // y(8n-113)
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,output signed [data_out_width-1 :0] IIRout_p8 // y(8n-128)
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,output signed [data_out_width-1 :0] IIRout_p9 // y(8n-143)
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,output signed [data_out_width-1 :0] IIRout_pa // y(8n-158)
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,output signed [data_out_width-1 :0] IIRout_pb // y(8n-173)
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,output signed [data_out_width-1 :0] IIRout_pc // y(8n-188)
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,output signed [data_out_width-1 :0] IIRout_pd // y(8n-203)
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,output signed [data_out_width-1 :0] IIRout_pe // y(8n-218)
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,output signed [data_out_width-1 :0] IIRout_pf // y(8n-233)
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);
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wire signed [b0_o_width- 1:0] IIRout_p0_re;
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wire signed [b1_o_width- 1:0] IIRout_p1_re;
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wire signed [b2_o_width- 1:0] IIRout_p2_re;
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wire signed [b3_o_width- 1:0] IIRout_p3_re;
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wire signed [b4_o_width- 1:0] IIRout_p4_re;
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wire signed [b5_o_width- 1:0] IIRout_p5_re;
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wire signed [b6_o_width- 1:0] IIRout_p6_re;
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wire signed [b7_o_width- 1:0] IIRout_p7_re;
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wire signed [b8_o_width- 1:0] IIRout_p8_re;
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wire signed [b9_o_width- 1:0] IIRout_p9_re;
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wire signed [b10_o_width- 1:0] IIRout_pa_re;
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wire signed [b11_o_width- 1:0] IIRout_pb_re;
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wire signed [b12_o_width- 1:0] IIRout_pc_re;
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wire signed [b13_o_width- 1:0] IIRout_pd_re;
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wire signed [b14_o_width- 1:0] IIRout_pe_re;
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wire signed [b15_o_width- 1:0] IIRout_pf_re;
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wire signed [b0_o_width- 1:0] IIRout_p0_im;
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wire signed [b1_o_width- 1:0] IIRout_p1_im;
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wire signed [b2_o_width- 1:0] IIRout_p2_im;
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wire signed [b3_o_width- 1:0] IIRout_p3_im;
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wire signed [b4_o_width- 1:0] IIRout_p4_im;
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wire signed [b5_o_width- 1:0] IIRout_p5_im;
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wire signed [b6_o_width- 1:0] IIRout_p6_im;
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wire signed [b7_o_width- 1:0] IIRout_p7_im;
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wire signed [b8_o_width- 1:0] IIRout_p8_im;
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wire signed [b9_o_width- 1:0] IIRout_p9_im;
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wire signed [b10_o_width- 1:0] IIRout_pa_im;
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wire signed [b11_o_width- 1:0] IIRout_pb_im;
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wire signed [b12_o_width- 1:0] IIRout_pc_im;
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wire signed [b13_o_width- 1:0] IIRout_pd_im;
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wire signed [b14_o_width- 1:0] IIRout_pe_im;
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wire signed [b15_o_width- 1:0] IIRout_pf_im;
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IIR_Filter_p16#(
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.coef_width ( coef_width ),
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.b_pow16_width ( b0_width ),
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.ab_pow_width ( a0_width ),
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.temp_var_width ( b0_i_width ),
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.data_out_width ( b0_o_width )
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)inst_iir_p0(
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.rstn ( rstn ),
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.clk ( clk ),
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.en ( en ),
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.dinp0 ( IIRin_pf ),
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.dinp1 ( IIRin_pe ),
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.dinp2 ( IIRin_pd ),
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.dinp3 ( IIRin_pc ),
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.dinp4 ( IIRin_pb ),
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.dinp5 ( IIRin_pa ),
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.dinp6 ( IIRin_p9 ),
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.dinp7 ( IIRin_p8 ),
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.dinp8 ( IIRin_p7 ),
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.dinp9 ( IIRin_p6 ),
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.dinpa ( IIRin_p5 ),
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.dinpb ( IIRin_p4 ),
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.dinpc ( IIRin_p3 ),
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.dinpd ( IIRin_p2 ),
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.dinpe ( IIRin_p1 ),
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.dinpf ( IIRin_p0 ),
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.a_re ( a_re ),
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.ab_re ( ab_re ),
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.abb_re ( abb_re ),
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.ab_pow3_re ( ab_pow3_re ),
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.ab_pow4_re ( ab_pow4_re ),
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.ab_pow5_re ( ab_pow5_re ),
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.ab_pow6_re ( ab_pow6_re ),
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.ab_pow7_re ( ab_pow7_re ),
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.ab_pow8_re ( ab_pow8_re ),
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.ab_pow9_re ( ab_pow9_re ),
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.ab_powa_re ( ab_powa_re ),
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.ab_powb_re ( ab_powb_re ),
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.ab_powc_re ( ab_powc_re ),
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.ab_powd_re ( ab_powd_re ),
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.ab_powe_re ( ab_powe_re ),
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.ab_powf_re ( ab_powf_re ),
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.b_pow16_re ( b_pow16_re ),
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.a_im ( a_im ),
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.ab_im ( ab_im ),
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.abb_im ( abb_im ),
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.ab_pow3_im ( ab_pow3_im ),
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.ab_pow4_im ( ab_pow4_im ),
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.ab_pow5_im ( ab_pow5_im ),
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.ab_pow6_im ( ab_pow6_im ),
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.ab_pow7_im ( ab_pow7_im ),
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.ab_pow8_im ( ab_pow8_im ),
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.ab_pow9_im ( ab_pow9_im ),
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.ab_powa_im ( ab_powa_im ),
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.ab_powb_im ( ab_powb_im ),
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.ab_powc_im ( ab_powc_im ),
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.ab_powd_im ( ab_powd_im ),
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.ab_powe_im ( ab_powe_im ),
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.ab_powf_im ( ab_powf_im ),
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.b_pow16_im ( b_pow16_im ),
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.dout_re ( IIRout_p0_re ),
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.dout_im ( IIRout_p0_im )
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);
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IIR_Filter_p1 #(
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.coef_width (coef_width ),
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.a_width (a1_width ),
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.b_width (b1_width ),
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.cascade_in_width (b1_i_width ),
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.data_out_width (b1_o_width )
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) inst_iir_p1(
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.din_re (IIRin_p0_r2 ), // x(8n-7)
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.dout_r1_re (IIRout_p0_re ), // Re(y(8n-8))
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.dout_r1_im (IIRout_p0_im ), // Re(y(8n-8))
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.a_re (a_re ),
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.b_re (b_re ),
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.dout_re (IIRout_p1_re ), // Re(y(8n-23))
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.a_im (a_im ),
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.b_im (b_im ),
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.dout_im (IIRout_p1_im ) // Re(y(8n-23))
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);
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IIR_Filter_p1 #(
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.coef_width (coef_width ),
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.a_width (a2_width ),
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.b_width (b2_width ),
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.cascade_in_width (b2_i_width ),
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.data_out_width (b2_o_width )
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) inst_iir_p2 (
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.din_re (IIRin_p1_r4 ), // x(8n-22)
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.dout_r1_re (IIRout_p1_re ), // Re(y(8n-23))
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.dout_r1_im (IIRout_p1_im ), // Re(y(8n-23))
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.a_re (a_re ),
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.b_re (b_re ),
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.dout_re (IIRout_p2_re ), // Re(y(8n-38))
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.a_im (a_im ),
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.b_im (b_im ),
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.dout_im (IIRout_p2_im ) // Re(y(8n-38))
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);
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IIR_Filter_p1 #(
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.coef_width (coef_width ),
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.a_width (a3_width ),
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.b_width (b3_width ),
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.cascade_in_width (b3_i_width ),
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.data_out_width (b3_o_width )
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) inst_iir_p3 (
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.din_re (IIRin_p2_r6 ), // x(8n-37)
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.dout_r1_re (IIRout_p2_re ), // Re(y(8n-38))
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.dout_r1_im (IIRout_p2_im ), // Re(y(8n-38))
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.a_re (a_re ),
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.b_re (b_re ),
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.dout_re (IIRout_p3_re ), // Re(y(8n-53))
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.a_im (a_im ),
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.b_im (b_im ),
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.dout_im (IIRout_p3_im ) // Re(y(8n-53))
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);
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IIR_Filter_p1 #(
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.coef_width (coef_width ),
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.a_width (a4_width ),
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.b_width (b4_width ),
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.cascade_in_width (b4_i_width ),
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.data_out_width (b4_o_width )
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) inst_iir_p4 (
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.din_re (IIRin_p3_r8 ), // x(8n-52)
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.dout_r1_re (IIRout_p3_re ), // Re(y(8n-53))
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.dout_r1_im (IIRout_p3_im ), // Re(y(8n-53))
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.a_re (a_re ),
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.b_re (b_re ),
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.dout_re (IIRout_p4_re ), // Re(y(8n-68))
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.a_im (a_im ),
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.b_im (b_im ),
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.dout_im (IIRout_p4_im ) // Re(y(8n-68))
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);
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IIR_Filter_p1 #(
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.coef_width (coef_width ),
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.a_width (a5_width ),
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.b_width (b5_width ),
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.cascade_in_width (b5_i_width ),
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.data_out_width (b5_o_width )
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) inst_iir_p5 (
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.din_re (IIRin_p4_r10 ), // x(8n-67)
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.dout_r1_re (IIRout_p4_re ), // Re(y(8n-68))
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.dout_r1_im (IIRout_p4_im ), // Re(y(8n-68))
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.a_re (a_re ),
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.b_re (b_re ),
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.dout_re (IIRout_p5_re ), // Re(y(8n-83))
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.a_im (a_im ),
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.b_im (b_im ),
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.dout_im (IIRout_p5_im ) // Re(y(8n-83))
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);
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IIR_Filter_p1 #(
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.coef_width (coef_width ),
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.a_width (a6_width ),
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.b_width (b6_width ),
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.cascade_in_width (b6_i_width ),
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|
.data_out_width (b6_o_width )
|
|
) inst_iir_p6 (
|
|
.clk (clk ),
|
|
.rstn (rstn ),
|
|
.en (en ),
|
|
.din_re (IIRin_p5_r12 ), // x(8n-82)
|
|
.dout_r1_re (IIRout_p5_re ), // Re(y(8n-83))
|
|
.dout_r1_im (IIRout_p5_im ), // Re(y(8n-83))
|
|
.a_re (a_re ),
|
|
.b_re (b_re ),
|
|
.dout_re (IIRout_p6_re ), // Re(y(8n-98))
|
|
.a_im (a_im ),
|
|
.b_im (b_im ),
|
|
.dout_im (IIRout_p6_im ) // Re(y(8n-98))
|
|
);
|
|
IIR_Filter_p1 #(
|
|
.coef_width (coef_width ),
|
|
.a_width (a7_width ),
|
|
.b_width (b7_width ),
|
|
.cascade_in_width (b7_i_width ),
|
|
.data_out_width (b7_o_width )
|
|
) inst_iir_p7 (
|
|
.clk (clk ),
|
|
.rstn (rstn ),
|
|
.en (en ),
|
|
.din_re (IIRin_p6_r14 ), // x(8n-97)
|
|
.dout_r1_re (IIRout_p6_re ), // Re(y(8n-98))
|
|
.a_re (a_re ),
|
|
.b_re (b_re ),
|
|
.dout_re (IIRout_p7_re ), // Re(y(8n-113))
|
|
.dout_r1_im (IIRout_p6_im ), // Re(y(8n-98))
|
|
.a_im (a_im ),
|
|
.b_im (b_im ),
|
|
.dout_im (IIRout_p7_im ) // Re(y(8n-113))
|
|
);
|
|
IIR_Filter_p1 #(
|
|
.coef_width (coef_width ),
|
|
.a_width (a8_width ),
|
|
.b_width (b8_width ),
|
|
.cascade_in_width (b8_i_width ),
|
|
.data_out_width (b8_o_width )
|
|
) inst_iir_p8 (
|
|
.clk (clk ),
|
|
.rstn (rstn ),
|
|
.en (en ),
|
|
.din_re (IIRin_p7_r16 ), // x(8n-112)
|
|
.dout_r1_re (IIRout_p7_re ), // Re(y(8n-113))
|
|
.dout_r1_im (IIRout_p7_im ), // Re(y(8n-113))
|
|
.a_re (a_re ),
|
|
.b_re (b_re ),
|
|
.dout_re (IIRout_p8_re ), // Re(y(8n-128))
|
|
.a_im (a_im ),
|
|
.b_im (b_im ),
|
|
.dout_im (IIRout_p8_im ) // Re(y(8n-128))
|
|
);
|
|
|
|
IIR_Filter_p1 #(
|
|
.coef_width (coef_width ),
|
|
.a_width (a9_width ),
|
|
.b_width (b9_width ),
|
|
.cascade_in_width (b9_i_width ),
|
|
.data_out_width (b9_o_width )
|
|
) inst_iir_p9 (
|
|
.clk (clk ),
|
|
.rstn (rstn ),
|
|
.en (en ),
|
|
.din_re (IIRin_p8_r18 ), // x(8n-127)
|
|
.dout_r1_re (IIRout_p8_re ), // Re(y(8n-128))
|
|
.dout_r1_im (IIRout_p8_im ), // Re(y(8n-128))
|
|
.a_re (a_re ),
|
|
.b_re (b_re ),
|
|
.dout_re (IIRout_p9_re ), // Re(y(8n-143))
|
|
.a_im (a_im ),
|
|
.b_im (b_im ),
|
|
.dout_im (IIRout_p9_im ) // Re(y(8n-143))
|
|
);
|
|
|
|
IIR_Filter_p1 #(
|
|
.coef_width (coef_width ),
|
|
.a_width (a10_width ),
|
|
.b_width (b10_width ),
|
|
.cascade_in_width (b10_i_width ),
|
|
.data_out_width (b10_o_width )
|
|
) inst_iir_pa (
|
|
.clk (clk ),
|
|
.rstn (rstn ),
|
|
.en (en ),
|
|
.din_re (IIRin_p9_r20 ), // x(8n-142)
|
|
.dout_r1_re (IIRout_p9_re ), // Re(y(8n-143))
|
|
.dout_r1_im (IIRout_p9_im ), // Re(y(8n-143))
|
|
.a_re (a_re ),
|
|
.b_re (b_re ),
|
|
.dout_re (IIRout_pa_re ), // Re(y(8n-158))
|
|
.a_im (a_im ),
|
|
.b_im (b_im ),
|
|
.dout_im (IIRout_pa_im ) // Re(y(8n-158))
|
|
);
|
|
|
|
IIR_Filter_p1 #(
|
|
.coef_width (coef_width ),
|
|
.a_width (a11_width ),
|
|
.b_width (b11_width ),
|
|
.cascade_in_width (b11_i_width ),
|
|
.data_out_width (b11_o_width )
|
|
) inst_iir_pb (
|
|
.clk (clk ),
|
|
.rstn (rstn ),
|
|
.en (en ),
|
|
.din_re (IIRin_pa_r22 ), // x(8n-157)
|
|
.dout_r1_re (IIRout_pa_re ), // Re(y(8n-158))
|
|
.dout_r1_im (IIRout_pa_im ), // Re(y(8n-158))
|
|
.a_re (a_re ),
|
|
.b_re (b_re ),
|
|
.dout_re (IIRout_pb_re ), // Re(y(8n-173))
|
|
.a_im (a_im ),
|
|
.b_im (b_im ),
|
|
.dout_im (IIRout_pb_im ) // Re(y(8n-173))
|
|
);
|
|
|
|
IIR_Filter_p1 #(
|
|
.coef_width (coef_width ),
|
|
.a_width (a12_width ),
|
|
.b_width (b12_width ),
|
|
.cascade_in_width (b12_i_width ),
|
|
.data_out_width (b12_o_width )
|
|
) inst_iir_pc (
|
|
.clk (clk ),
|
|
.rstn (rstn ),
|
|
.en (en ),
|
|
.din_re (IIRin_pb_r24 ), // x(8n-172)
|
|
.dout_r1_re (IIRout_pb_re ), // Re(y(8n-173))
|
|
.dout_r1_im (IIRout_pb_im ), // Re(y(8n-173))
|
|
.a_re (a_re ),
|
|
.b_re (b_re ),
|
|
.dout_re (IIRout_pc_re ), // Re(y(8n-188))
|
|
.a_im (a_im ),
|
|
.b_im (b_im ),
|
|
.dout_im (IIRout_pc_im ) // Re(y(8n-188))
|
|
);
|
|
|
|
IIR_Filter_p1 #(
|
|
.coef_width (coef_width ),
|
|
.a_width (a13_width ),
|
|
.b_width (b13_width ),
|
|
.cascade_in_width (b13_i_width ),
|
|
.data_out_width (b13_o_width )
|
|
) inst_iir_pd (
|
|
.clk (clk ),
|
|
.rstn (rstn ),
|
|
.en (en ),
|
|
.din_re (IIRin_pc_r26 ), // x(8n-187)
|
|
.dout_r1_re (IIRout_pc_re ), // Re(y(8n-188))
|
|
.dout_r1_im (IIRout_pc_im ), // Re(y(8n-188))
|
|
.a_re (a_re ),
|
|
.b_re (b_re ),
|
|
.dout_re (IIRout_pd_re ), // Re(y(8n-203))
|
|
.a_im (a_im ),
|
|
.b_im (b_im ),
|
|
.dout_im (IIRout_pd_im ) // Re(y(8n-203))
|
|
);
|
|
|
|
IIR_Filter_p1 #(
|
|
.coef_width (coef_width ),
|
|
.a_width (a14_width ),
|
|
.b_width (b14_width ),
|
|
.cascade_in_width (b14_i_width ),
|
|
.data_out_width (b14_o_width )
|
|
) inst_iir_pe (
|
|
.clk (clk ),
|
|
.rstn (rstn ),
|
|
.en (en ),
|
|
.din_re (IIRin_pd_r28 ), // x(8n-202)
|
|
.dout_r1_re (IIRout_pd_re ), // Re(y(8n-203))
|
|
.dout_r1_im (IIRout_pd_im ), // Re(y(8n-203))
|
|
.a_re (a_re ),
|
|
.b_re (b_re ),
|
|
.dout_re (IIRout_pe_re ), // Re(y(8n-218))
|
|
.a_im (a_im ),
|
|
.b_im (b_im ),
|
|
.dout_im (IIRout_pe_im ) // Re(y(8n-218))
|
|
);
|
|
|
|
IIR_Filter_p1 #(
|
|
.coef_width (coef_width ),
|
|
.a_width (a15_width ),
|
|
.b_width (b15_width ),
|
|
.cascade_in_width (b15_i_width ),
|
|
.data_out_width (b15_o_width )
|
|
) inst_iir_pf (
|
|
.clk (clk ),
|
|
.rstn (rstn ),
|
|
.en (en ),
|
|
.din_re (IIRin_pe_r30 ), // x(8n-217)
|
|
.dout_r1_re (IIRout_pe_re ), // Re(y(8n-218))
|
|
.dout_r1_im (IIRout_pe_im ), // Re(y(8n-218))
|
|
.a_re (a_re ),
|
|
.b_re (b_re ),
|
|
.dout_re (IIRout_pf_re ), // Re(y(8n-233))
|
|
.a_im (a_im ),
|
|
.b_im (b_im ),
|
|
.dout_im (IIRout_pf_im ) // Re(y(8n-233))
|
|
);
|
|
|
|
|
|
assign IIRout_p0 = IIRout_p0_re[b0_o_width-1 : b0_o_width-data_out_width]; // y(8n-8)
|
|
assign IIRout_p1 = IIRout_p1_re[b1_o_width-1 : b1_o_width-data_out_width]; // y(8n-23)
|
|
assign IIRout_p2 = IIRout_p2_re[b2_o_width-1 : b2_o_width-data_out_width]; // y(8n-38)
|
|
assign IIRout_p3 = IIRout_p3_re[b3_o_width-1 : b3_o_width-data_out_width]; // y(8n-53)
|
|
assign IIRout_p4 = IIRout_p4_re[b4_o_width-1 : b4_o_width-data_out_width]; // y(8n-68)
|
|
assign IIRout_p5 = IIRout_p5_re[b5_o_width-1 : b5_o_width-data_out_width]; // y(8n-83)
|
|
assign IIRout_p6 = IIRout_p6_re[b6_o_width-1 : b6_o_width-data_out_width]; // y(8n-98)
|
|
assign IIRout_p7 = IIRout_p7_re[b7_o_width-1 : b7_o_width-data_out_width]; // y(8n-113)
|
|
assign IIRout_p8 = IIRout_p8_re[b8_o_width-1 : b8_o_width-data_out_width]; // y(8n-128)
|
|
assign IIRout_p9 = IIRout_p9_re[b9_o_width-1 : b9_o_width-data_out_width]; // y(8n-143)
|
|
assign IIRout_pa = IIRout_pa_re[b10_o_width-1 : b10_o_width-data_out_width]; // y(8n-158)
|
|
assign IIRout_pb = IIRout_pb_re[b11_o_width-1 : b11_o_width-data_out_width]; // y(8n-173)
|
|
assign IIRout_pc = IIRout_pc_re[b12_o_width-1 : b12_o_width-data_out_width]; // y(8n-188)
|
|
assign IIRout_pd = IIRout_pd_re[b13_o_width-1 : b13_o_width-data_out_width]; // y(8n-203)
|
|
assign IIRout_pe = IIRout_pe_re[b14_o_width-1 : b14_o_width-data_out_width]; // y(8n-218)
|
|
assign IIRout_pf = IIRout_pf_re[b15_o_width-1 : b15_o_width-data_out_width]; // y(8n-233)
|
|
|
|
endmodule
|
|
|