824 lines
28 KiB
Systemverilog
824 lines
28 KiB
Systemverilog
module CoefGen #(
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parameter data_in_width = 32
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,parameter coef_width = 32
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,parameter frac_data_out_width = 20//X for in,5
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,parameter frac_coef_width = 31//division
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)
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(
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input rstn
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,input clk
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,input [3:0] vldi
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,input signed [31:0] a0_re
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,input signed [31:0] b0_re
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,input signed [31:0] a1_re
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,input signed [31:0] b1_re
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,input signed [31:0] a2_re
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,input signed [31:0] b2_re
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,input signed [31:0] a3_re
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,input signed [31:0] b3_re
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,input signed [31:0] a0_im
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,input signed [31:0] b0_im
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,input signed [31:0] a1_im
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,input signed [31:0] b1_im
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,input signed [31:0] a2_im
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,input signed [31:0] b2_im
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,input signed [31:0] a3_im
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,input signed [31:0] b3_im
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,output reg signed [31:0] a_re0
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,output reg signed [31:0] b_re0
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,output reg signed [31:0] ab_re0
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,output reg signed [31:0] abb_re0
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,output reg signed [31:0] ab_pow3_re0
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,output reg signed [31:0] ab_pow4_re0
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,output reg signed [31:0] ab_pow5_re0
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,output reg signed [31:0] ab_pow6_re0
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,output reg signed [31:0] ab_pow7_re0
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,output reg signed [31:0] ab_pow8_re0
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,output reg signed [31:0] ab_pow9_re0
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,output reg signed [31:0] ab_powa_re0
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,output reg signed [31:0] ab_powb_re0
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,output reg signed [31:0] ab_powc_re0
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,output reg signed [31:0] ab_powd_re0
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,output reg signed [31:0] ab_powe_re0
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,output reg signed [31:0] ab_powf_re0
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,output reg signed [31:0] b_pow16_re0
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,output reg signed [31:0] a_re1
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,output reg signed [31:0] b_re1
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,output reg signed [31:0] ab_re1
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,output reg signed [31:0] abb_re1
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,output reg signed [31:0] ab_pow3_re1
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,output reg signed [31:0] ab_pow4_re1
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,output reg signed [31:0] ab_pow5_re1
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,output reg signed [31:0] ab_pow6_re1
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,output reg signed [31:0] ab_pow7_re1
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,output reg signed [31:0] ab_pow8_re1
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,output reg signed [31:0] ab_pow9_re1
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,output reg signed [31:0] ab_powa_re1
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,output reg signed [31:0] ab_powb_re1
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,output reg signed [31:0] ab_powc_re1
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,output reg signed [31:0] ab_powd_re1
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,output reg signed [31:0] ab_powe_re1
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,output reg signed [31:0] ab_powf_re1
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,output reg signed [31:0] b_pow16_re1
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,output reg signed [31:0] a_re2
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,output reg signed [31:0] b_re2
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,output reg signed [31:0] ab_re2
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,output reg signed [31:0] abb_re2
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,output reg signed [31:0] ab_pow3_re2
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,output reg signed [31:0] ab_pow4_re2
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,output reg signed [31:0] ab_pow5_re2
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,output reg signed [31:0] ab_pow6_re2
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,output reg signed [31:0] ab_pow7_re2
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,output reg signed [31:0] ab_pow8_re2
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,output reg signed [31:0] ab_pow9_re2
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,output reg signed [31:0] ab_powa_re2
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,output reg signed [31:0] ab_powb_re2
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,output reg signed [31:0] ab_powc_re2
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,output reg signed [31:0] ab_powd_re2
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,output reg signed [31:0] ab_powe_re2
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,output reg signed [31:0] ab_powf_re2
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,output reg signed [31:0] b_pow16_re2
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,output reg signed [31:0] a_re3
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,output reg signed [31:0] b_re3
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,output reg signed [31:0] ab_re3
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,output reg signed [31:0] abb_re3
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,output reg signed [31:0] ab_pow3_re3
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,output reg signed [31:0] ab_pow4_re3
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,output reg signed [31:0] ab_pow5_re3
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,output reg signed [31:0] ab_pow6_re3
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,output reg signed [31:0] ab_pow7_re3
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,output reg signed [31:0] ab_pow8_re3
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,output reg signed [31:0] ab_pow9_re3
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,output reg signed [31:0] ab_powa_re3
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,output reg signed [31:0] ab_powb_re3
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,output reg signed [31:0] ab_powc_re3
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,output reg signed [31:0] ab_powd_re3
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,output reg signed [31:0] ab_powe_re3
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,output reg signed [31:0] ab_powf_re3
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,output reg signed [31:0] b_pow16_re3
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,output reg signed [31:0] a_im0
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,output reg signed [31:0] b_im0
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,output reg signed [31:0] ab_im0
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,output reg signed [31:0] abb_im0
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,output reg signed [31:0] ab_pow3_im0
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,output reg signed [31:0] ab_pow4_im0
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,output reg signed [31:0] ab_pow5_im0
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,output reg signed [31:0] ab_pow6_im0
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,output reg signed [31:0] ab_pow7_im0
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,output reg signed [31:0] ab_pow8_im0
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,output reg signed [31:0] ab_pow9_im0
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,output reg signed [31:0] ab_powa_im0
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,output reg signed [31:0] ab_powb_im0
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,output reg signed [31:0] ab_powc_im0
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,output reg signed [31:0] ab_powd_im0
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,output reg signed [31:0] ab_powe_im0
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,output reg signed [31:0] ab_powf_im0
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,output reg signed [31:0] b_pow16_im0
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,output reg signed [31:0] a_im1
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,output reg signed [31:0] b_im1
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,output reg signed [31:0] ab_im1
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,output reg signed [31:0] abb_im1
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,output reg signed [31:0] ab_pow3_im1
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,output reg signed [31:0] ab_pow4_im1
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,output reg signed [31:0] ab_pow5_im1
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,output reg signed [31:0] ab_pow6_im1
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,output reg signed [31:0] ab_pow7_im1
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,output reg signed [31:0] ab_pow8_im1
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,output reg signed [31:0] ab_pow9_im1
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,output reg signed [31:0] ab_powa_im1
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,output reg signed [31:0] ab_powb_im1
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,output reg signed [31:0] ab_powc_im1
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,output reg signed [31:0] ab_powd_im1
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,output reg signed [31:0] ab_powe_im1
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,output reg signed [31:0] ab_powf_im1
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,output reg signed [31:0] b_pow16_im1
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,output reg signed [31:0] a_im2
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,output reg signed [31:0] b_im2
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,output reg signed [31:0] ab_im2
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,output reg signed [31:0] abb_im2
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,output reg signed [31:0] ab_pow3_im2
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,output reg signed [31:0] ab_pow4_im2
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,output reg signed [31:0] ab_pow5_im2
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,output reg signed [31:0] ab_pow6_im2
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,output reg signed [31:0] ab_pow7_im2
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,output reg signed [31:0] ab_pow8_im2
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,output reg signed [31:0] ab_pow9_im2
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,output reg signed [31:0] ab_powa_im2
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,output reg signed [31:0] ab_powb_im2
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,output reg signed [31:0] ab_powc_im2
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,output reg signed [31:0] ab_powd_im2
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,output reg signed [31:0] ab_powe_im2
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,output reg signed [31:0] ab_powf_im2
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,output reg signed [31:0] b_pow16_im2
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,output reg signed [31:0] a_im3
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,output reg signed [31:0] b_im3
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,output reg signed [31:0] ab_im3
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,output reg signed [31:0] abb_im3
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,output reg signed [31:0] ab_pow3_im3
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,output reg signed [31:0] ab_pow4_im3
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,output reg signed [31:0] ab_pow5_im3
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,output reg signed [31:0] ab_pow6_im3
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,output reg signed [31:0] ab_pow7_im3
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,output reg signed [31:0] ab_pow8_im3
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,output reg signed [31:0] ab_pow9_im3
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,output reg signed [31:0] ab_powa_im3
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,output reg signed [31:0] ab_powb_im3
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,output reg signed [31:0] ab_powc_im3
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,output reg signed [31:0] ab_powd_im3
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,output reg signed [31:0] ab_powe_im3
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,output reg signed [31:0] ab_powf_im3
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,output reg signed [31:0] b_pow16_im3
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);
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reg vldi_or_r1;
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wire vldi_or = | vldi;
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sirv_gnrl_dffr #(1) dff_vldi_or_1(vldi_or, vldi_or_r1 ,clk,rstn);
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reg signed [data_in_width-1:0] a_re_r1;
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reg signed [data_in_width-1:0] b_re_r1;
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reg signed [data_in_width-1:0] a_im_r1;
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reg signed [data_in_width-1:0] b_im_r1;
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always @(posedge clk or negedge rstn) begin
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if(rstn == 1'b0) begin
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a_re_r1 <= 'h0;
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b_re_r1 <= 'h0;
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end
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else if(|vldi) begin
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case(1'b1)
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vldi[0]: begin
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a_re_r1 <= a0_re;
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b_re_r1 <= b0_re;
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a_im_r1 <= a0_im;
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b_im_r1 <= b0_im;
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end
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vldi[1]: begin
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a_re_r1 <= a1_re;
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b_re_r1 <= b1_re;
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a_im_r1 <= a1_im;
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b_im_r1 <= b1_im;
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end
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vldi[2]: begin
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a_re_r1 <= a2_re;
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b_re_r1 <= b2_re;
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a_im_r1 <= a2_im;
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b_im_r1 <= b2_im;
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end
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vldi[3]: begin
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a_re_r1 <= a3_re;
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b_re_r1 <= b3_re;
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a_im_r1 <= a3_im;
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b_im_r1 <= b3_im;
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end
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// default: begin
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// a_re_r1 <= a_re[0];
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// b_re_r1 <= b_re[0];
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// end
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endcase
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end
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end
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reg en;
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reg en_r1;
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sirv_gnrl_dffr #(1) dff_en_1(en, en_r1 ,clk,rstn);
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reg [4:0] cnt0;
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wire add_cnt0;
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wire end_cnt0;
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always @(posedge clk or negedge rstn)begin
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if(!rstn)begin
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cnt0 <= 0;
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end
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else if(add_cnt0)begin
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if(end_cnt0)
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cnt0 <= 0;
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else
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cnt0 <= cnt0 + 1;
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end
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end
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assign add_cnt0 = en;
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assign end_cnt0 = add_cnt0 && cnt0== 16-1;
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wire en_l;
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wire en_h;
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always @(posedge clk or negedge rstn)begin
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if(rstn==1'b0)begin
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en <= 0;
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end
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else if(en_h)begin
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en <= 1;
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end
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else if(en_l)begin
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en <= 0;
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end
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end
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assign en_h = vldi_or == 1 && vldi_or_r1 == 0 && cnt0 == 0;
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assign en_l = end_cnt0;
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reg signed [data_in_width-1:0] bin_re;
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wire signed [data_in_width-1:0] bout_re;
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reg signed [data_in_width-1:0] bin_im;
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wire signed [data_in_width-1:0] bout_im;
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always @(*)begin
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if(en_r1) begin
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bin_re <= bout_re;
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bin_im <= bout_im;
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end
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else begin
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bin_re <= 32'd2147483647;
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bin_im <= 0;
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end
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end
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mult_C
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#(
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.A_width(data_in_width)
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,.B_width(data_in_width)
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,.C_width(coef_width)
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,.D_width(coef_width)
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,.o_width(data_in_width)
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)
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inst_c1 (
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.a (bin_re ),
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.b (bin_im ),
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.c (b_re_r1 ),
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.d (b_im_r1 ),
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.Re (bout_re ),
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.Im (bout_im )
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);
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wire signed [data_in_width-1:0] abo_re;
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wire signed [data_in_width-1:0] abo_im;
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mult_C
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#(
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.A_width(data_in_width)
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,.B_width(data_in_width)
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,.C_width(coef_width)
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,.D_width(coef_width)
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,.o_width(data_in_width)
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)
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inst_c2 (
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.a (bin_re ),
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.b (bin_im ),
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.c (a_re_r1 ),
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.d (a_im_r1 ),
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.Re (abo_re ),
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.Im (abo_im )
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);
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reg signed [coef_width-1 :0] ao_re_r1 ;
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reg signed [coef_width-1 :0] ab_re_r1 ;
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reg signed [coef_width-1 :0] abb_re_r1 ;
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reg signed [coef_width-1 :0] ab_pow3_re_r1;
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reg signed [coef_width-1 :0] ab_pow4_re_r1;
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reg signed [coef_width-1 :0] ab_pow5_re_r1;
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reg signed [coef_width-1 :0] ab_pow6_re_r1;
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reg signed [coef_width-1 :0] ab_pow7_re_r1;
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reg signed [coef_width-1 :0] ab_pow8_re_r1;
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reg signed [coef_width-1 :0] ab_pow9_re_r1;
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reg signed [coef_width-1 :0] ab_powa_re_r1;
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reg signed [coef_width-1 :0] ab_powb_re_r1;
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reg signed [coef_width-1 :0] ab_powc_re_r1;
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reg signed [coef_width-1 :0] ab_powd_re_r1;
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reg signed [coef_width-1 :0] ab_powe_re_r1;
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reg signed [coef_width-1 :0] ab_powf_re_r1;
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reg signed [coef_width-1 :0] bo_re_r1 ;
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reg signed [coef_width-1 :0] b_pow16_re_r1 ;
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reg signed [coef_width-1 :0] ao_im_r1 ;
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reg signed [coef_width-1 :0] ab_im_r1 ;
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reg signed [coef_width-1 :0] abb_im_r1 ;
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reg signed [coef_width-1 :0] ab_pow3_im_r1;
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reg signed [coef_width-1 :0] ab_pow4_im_r1;
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reg signed [coef_width-1 :0] ab_pow5_im_r1;
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reg signed [coef_width-1 :0] ab_pow6_im_r1;
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reg signed [coef_width-1 :0] ab_pow7_im_r1;
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reg signed [coef_width-1 :0] ab_pow8_im_r1;
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reg signed [coef_width-1 :0] ab_pow9_im_r1;
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reg signed [coef_width-1 :0] ab_powa_im_r1;
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reg signed [coef_width-1 :0] ab_powb_im_r1;
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reg signed [coef_width-1 :0] ab_powc_im_r1;
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reg signed [coef_width-1 :0] ab_powd_im_r1;
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reg signed [coef_width-1 :0] ab_powe_im_r1;
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reg signed [coef_width-1 :0] ab_powf_im_r1;
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reg signed [coef_width-1 :0] bo_im_r1 ;
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reg signed [coef_width-1 :0] b_pow16_im_r1 ;
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always @(posedge clk or negedge rstn)begin
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if(!rstn)begin
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ao_re_r1 <= 0;
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ab_re_r1 <= 0;
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abb_re_r1 <= 0;
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ab_pow3_re_r1 <= 0;
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ab_pow4_re_r1 <= 0;
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ab_pow5_re_r1 <= 0;
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ab_pow6_re_r1 <= 0;
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ab_pow7_re_r1 <= 0;
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ab_pow8_re_r1 <= 0;
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ab_pow9_re_r1 <= 0;
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ab_powa_re_r1 <= 0;
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ab_powb_re_r1 <= 0;
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ab_powc_re_r1 <= 0;
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ab_powd_re_r1 <= 0;
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ab_powe_re_r1 <= 0;
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ab_powf_re_r1 <= 0;
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bo_re_r1 <= 0;
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b_pow16_re_r1 <= 0;
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ao_im_r1 <= 0;
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ab_im_r1 <= 0;
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abb_im_r1 <= 0;
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ab_pow3_im_r1 <= 0;
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ab_pow4_im_r1 <= 0;
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ab_pow5_im_r1 <= 0;
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ab_pow6_im_r1 <= 0;
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ab_pow7_im_r1 <= 0;
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ab_pow8_im_r1 <= 0;
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ab_pow9_im_r1 <= 0;
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ab_powa_im_r1 <= 0;
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ab_powb_im_r1 <= 0;
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ab_powc_im_r1 <= 0;
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ab_powd_im_r1 <= 0;
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ab_powe_im_r1 <= 0;
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ab_powf_im_r1 <= 0;
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bo_im_r1 <= 0;
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b_pow16_im_r1 <= 0;
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end
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else if(add_cnt0 && cnt0 == 1 && en_r1)begin
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ao_re_r1 <= abo_re;
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bo_re_r1 <= bin_re;
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ao_im_r1 <= abo_im;
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bo_im_r1 <= bin_im;
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end
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else if(add_cnt0 && cnt0 == 2 && en_r1)begin
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ab_re_r1 <= abo_re;
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ab_im_r1 <= abo_im;
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end
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else if(add_cnt0 && cnt0 == 3 && en_r1)begin
|
|
abb_re_r1 <= abo_re;
|
|
abb_im_r1 <= abo_im;
|
|
end
|
|
else if(add_cnt0 && cnt0 == 4 && en_r1)begin
|
|
ab_pow3_re_r1 <= abo_re;
|
|
ab_pow3_im_r1 <= abo_im;
|
|
end
|
|
else if(add_cnt0 && cnt0 == 5 && en_r1)begin
|
|
ab_pow4_re_r1 <= abo_re;
|
|
ab_pow4_im_r1 <= abo_im;
|
|
end
|
|
else if(add_cnt0 && cnt0 == 6 && en_r1)begin
|
|
ab_pow5_re_r1 <= abo_re;
|
|
ab_pow5_im_r1 <= abo_im;
|
|
end
|
|
else if(add_cnt0 && cnt0 == 7 && en_r1)begin
|
|
ab_pow6_re_r1 <= abo_re;
|
|
ab_pow6_im_r1 <= abo_im;
|
|
end
|
|
else if(add_cnt0 && cnt0 == 8 && en_r1)begin
|
|
ab_pow7_re_r1 <= abo_re;
|
|
ab_pow7_im_r1 <= abo_im;
|
|
end
|
|
else if(add_cnt0 && cnt0 == 9 && en_r1)begin
|
|
ab_pow8_re_r1 <= abo_re;
|
|
ab_pow8_im_r1 <= abo_im;
|
|
end
|
|
else if(add_cnt0 && cnt0 == 10 && en_r1)begin
|
|
ab_pow9_re_r1 <= abo_re;
|
|
ab_pow9_im_r1 <= abo_im;
|
|
end
|
|
else if(add_cnt0 && cnt0 == 11 && en_r1)begin
|
|
ab_powa_re_r1 <= abo_re;
|
|
ab_powa_im_r1 <= abo_im;
|
|
end
|
|
else if(add_cnt0 && cnt0 == 12 && en_r1)begin
|
|
ab_powb_re_r1 <= abo_re;
|
|
ab_powb_im_r1 <= abo_im;
|
|
end
|
|
else if(add_cnt0 && cnt0 == 13 && en_r1)begin
|
|
ab_powc_re_r1 <= abo_re;
|
|
ab_powc_im_r1 <= abo_im;
|
|
end
|
|
else if(add_cnt0 && cnt0 == 14 && en_r1)begin
|
|
ab_powd_re_r1 <= abo_re;
|
|
ab_powd_im_r1 <= abo_im;
|
|
end
|
|
else if(add_cnt0 && cnt0 == 15 && en_r1)begin
|
|
ab_powe_re_r1 <= abo_re;
|
|
ab_powe_im_r1 <= abo_im;
|
|
end
|
|
else if(cnt0 == 0 && en_r1)begin
|
|
ab_powf_re_r1 <= abo_re;
|
|
b_pow16_re_r1 <= bin_re;
|
|
ab_powf_im_r1 <= abo_im;
|
|
b_pow16_im_r1 <= bin_im;
|
|
end
|
|
|
|
// else begin
|
|
// end
|
|
end
|
|
|
|
reg [3:0] vldi_r1;
|
|
reg [3:0] vldi_r2;
|
|
reg [3:0] vldi_r3;
|
|
reg [3:0] vldi_r4;
|
|
reg [3:0] vldi_r5;
|
|
reg [3:0] vldi_r6;
|
|
reg [3:0] vldi_r7;
|
|
reg [3:0] vldi_r8;
|
|
reg [3:0] vldi_r9;
|
|
reg [3:0] vldi_r10;
|
|
reg [3:0] vldi_r11;
|
|
reg [3:0] vldi_r12;
|
|
reg [3:0] vldi_r13;
|
|
reg [3:0] vldi_r14;
|
|
reg [3:0] vldi_r15;
|
|
reg [3:0] vldi_r16;
|
|
reg [3:0] vldi_r17;
|
|
reg [3:0] vldi_r18;
|
|
//syncer #(6, 10) sync_vldo_syncer (clk, rstn, vldi, vldi_r10);
|
|
sirv_gnrl_dffr #(4) dff_vldi_1(vldi,vldi_r1,clk,rstn);
|
|
sirv_gnrl_dffr #(4) dff_vldi_2(vldi_r1, vldi_r2 ,clk,rstn);
|
|
sirv_gnrl_dffr #(4) dff_vldi_3(vldi_r2, vldi_r3 ,clk,rstn);
|
|
sirv_gnrl_dffr #(4) dff_vldi_4(vldi_r3, vldi_r4 ,clk,rstn);
|
|
sirv_gnrl_dffr #(4) dff_vldi_5(vldi_r4, vldi_r5 ,clk,rstn);
|
|
sirv_gnrl_dffr #(4) dff_vldi_6(vldi_r5, vldi_r6 ,clk,rstn);
|
|
sirv_gnrl_dffr #(4) dff_vldi_7(vldi_r6, vldi_r7 ,clk,rstn);
|
|
sirv_gnrl_dffr #(4) dff_vldi_8(vldi_r7, vldi_r8 ,clk,rstn);
|
|
sirv_gnrl_dffr #(4) dff_vldi_9(vldi_r8, vldi_r9 ,clk,rstn);
|
|
sirv_gnrl_dffr #(4) dff_vldi_10(vldi_r9, vldi_r10,clk,rstn);
|
|
sirv_gnrl_dffr #(4) dff_vldi_11(vldi_r10, vldi_r11,clk,rstn);
|
|
sirv_gnrl_dffr #(4) dff_vldi_12(vldi_r11, vldi_r12,clk,rstn);
|
|
sirv_gnrl_dffr #(4) dff_vldi_13(vldi_r12, vldi_r13,clk,rstn);
|
|
sirv_gnrl_dffr #(4) dff_vldi_14(vldi_r13, vldi_r14,clk,rstn);
|
|
sirv_gnrl_dffr #(4) dff_vldi_15(vldi_r14, vldi_r15,clk,rstn);
|
|
sirv_gnrl_dffr #(4) dff_vldi_16(vldi_r15, vldi_r16,clk,rstn);
|
|
sirv_gnrl_dffr #(4) dff_vldi_17(vldi_r16, vldi_r17,clk,rstn);
|
|
sirv_gnrl_dffr #(4) dff_vldi_18(vldi_r17, vldi_r18,clk,rstn);
|
|
always @(posedge clk or negedge rstn) begin
|
|
if(!rstn) begin
|
|
a_re0 <= 0;
|
|
b_re0 <= 0;
|
|
ab_re0 <= 0;
|
|
abb_re0 <= 0;
|
|
ab_pow3_re0 <= 0;
|
|
ab_pow4_re0 <= 0;
|
|
ab_pow5_re0 <= 0;
|
|
ab_pow6_re0 <= 0;
|
|
ab_pow7_re0 <= 0;
|
|
ab_pow8_re0 <= 0;
|
|
ab_pow9_re0 <= 0;
|
|
ab_powa_re0 <= 0;
|
|
ab_powb_re0 <= 0;
|
|
ab_powc_re0 <= 0;
|
|
ab_powd_re0 <= 0;
|
|
ab_powe_re0 <= 0;
|
|
ab_powf_re0 <= 0;
|
|
b_pow16_re0 <= 0;
|
|
a_re1 <= 0;
|
|
b_re1 <= 0;
|
|
ab_re1 <= 0;
|
|
abb_re1 <= 0;
|
|
ab_pow3_re1 <= 0;
|
|
ab_pow4_re1 <= 0;
|
|
ab_pow5_re1 <= 0;
|
|
ab_pow6_re1 <= 0;
|
|
ab_pow7_re1 <= 0;
|
|
ab_pow8_re1 <= 0;
|
|
ab_pow9_re1 <= 0;
|
|
ab_powa_re1 <= 0;
|
|
ab_powb_re1 <= 0;
|
|
ab_powc_re1 <= 0;
|
|
ab_powd_re1 <= 0;
|
|
ab_powe_re1 <= 0;
|
|
ab_powf_re1 <= 0;
|
|
b_pow16_re1 <= 0;
|
|
a_re2 <= 0;
|
|
b_re2 <= 0;
|
|
ab_re2 <= 0;
|
|
abb_re2 <= 0;
|
|
ab_pow3_re2 <= 0;
|
|
ab_pow4_re2 <= 0;
|
|
ab_pow5_re2 <= 0;
|
|
ab_pow6_re2 <= 0;
|
|
ab_pow7_re2 <= 0;
|
|
ab_pow8_re2 <= 0;
|
|
ab_pow9_re2 <= 0;
|
|
ab_powa_re2 <= 0;
|
|
ab_powb_re2 <= 0;
|
|
ab_powc_re2 <= 0;
|
|
ab_powd_re2 <= 0;
|
|
ab_powe_re2 <= 0;
|
|
ab_powf_re2 <= 0;
|
|
b_pow16_re2 <= 0;
|
|
a_re3 <= 0;
|
|
b_re3 <= 0;
|
|
ab_re3 <= 0;
|
|
abb_re3 <= 0;
|
|
ab_pow3_re3 <= 0;
|
|
ab_pow4_re3 <= 0;
|
|
ab_pow5_re3 <= 0;
|
|
ab_pow6_re3 <= 0;
|
|
ab_pow7_re3 <= 0;
|
|
ab_pow8_re3 <= 0;
|
|
ab_pow9_re3 <= 0;
|
|
ab_powa_re3 <= 0;
|
|
ab_powb_re3 <= 0;
|
|
ab_powc_re3 <= 0;
|
|
ab_powd_re3 <= 0;
|
|
ab_powe_re3 <= 0;
|
|
ab_powf_re3 <= 0;
|
|
b_pow16_re3 <= 0;
|
|
a_im0 <= 0;
|
|
b_im0 <= 0;
|
|
ab_im0 <= 0;
|
|
abb_im0 <= 0;
|
|
ab_pow3_im0 <= 0;
|
|
ab_pow4_im0 <= 0;
|
|
ab_pow5_im0 <= 0;
|
|
ab_pow6_im0 <= 0;
|
|
ab_pow7_im0 <= 0;
|
|
ab_pow8_im0 <= 0;
|
|
ab_pow9_im0 <= 0;
|
|
ab_powa_im0 <= 0;
|
|
ab_powb_im0 <= 0;
|
|
ab_powc_im0 <= 0;
|
|
ab_powd_im0 <= 0;
|
|
ab_powe_im0 <= 0;
|
|
ab_powf_im0 <= 0;
|
|
b_pow16_im0 <= 0;
|
|
a_im1 <= 0;
|
|
b_im1 <= 0;
|
|
ab_im1 <= 0;
|
|
abb_im1 <= 0;
|
|
ab_pow3_im1 <= 0;
|
|
ab_pow4_im1 <= 0;
|
|
ab_pow5_im1 <= 0;
|
|
ab_pow6_im1 <= 0;
|
|
ab_pow7_im1 <= 0;
|
|
ab_pow8_im1 <= 0;
|
|
ab_pow9_im1 <= 0;
|
|
ab_powa_im1 <= 0;
|
|
ab_powb_im1 <= 0;
|
|
ab_powc_im1 <= 0;
|
|
ab_powd_im1 <= 0;
|
|
ab_powe_im1 <= 0;
|
|
ab_powf_im1 <= 0;
|
|
b_pow16_im1 <= 0;
|
|
a_im2 <= 0;
|
|
b_im2 <= 0;
|
|
ab_im2 <= 0;
|
|
abb_im2 <= 0;
|
|
ab_pow3_im2 <= 0;
|
|
ab_pow4_im2 <= 0;
|
|
ab_pow5_im2 <= 0;
|
|
ab_pow6_im2 <= 0;
|
|
ab_pow7_im2 <= 0;
|
|
ab_pow8_im2 <= 0;
|
|
ab_pow9_im2 <= 0;
|
|
ab_powa_im2 <= 0;
|
|
ab_powb_im2 <= 0;
|
|
ab_powc_im2 <= 0;
|
|
ab_powd_im2 <= 0;
|
|
ab_powe_im2 <= 0;
|
|
ab_powf_im2 <= 0;
|
|
b_pow16_im2 <= 0;
|
|
a_im3 <= 0;
|
|
b_im3 <= 0;
|
|
ab_im3 <= 0;
|
|
abb_im3 <= 0;
|
|
ab_pow3_im3 <= 0;
|
|
ab_pow4_im3 <= 0;
|
|
ab_pow5_im3 <= 0;
|
|
ab_pow6_im3 <= 0;
|
|
ab_pow7_im3 <= 0;
|
|
ab_pow8_im3 <= 0;
|
|
ab_pow9_im3 <= 0;
|
|
ab_powa_im3 <= 0;
|
|
ab_powb_im3 <= 0;
|
|
ab_powc_im3 <= 0;
|
|
ab_powd_im3 <= 0;
|
|
ab_powe_im3 <= 0;
|
|
ab_powf_im3 <= 0;
|
|
b_pow16_im3 <= 0;
|
|
end
|
|
else if(|vldi_r18) begin
|
|
case(1'b1)
|
|
vldi_r18[0]: begin
|
|
a_re0 <= ao_re_r1 ;
|
|
b_re0 <= bo_re_r1 ;
|
|
ab_re0 <= ab_re_r1 ;
|
|
abb_re0 <= abb_re_r1 ;
|
|
ab_pow3_re0 <= ab_pow3_re_r1;
|
|
ab_pow4_re0 <= ab_pow4_re_r1;
|
|
ab_pow5_re0 <= ab_pow5_re_r1;
|
|
ab_pow6_re0 <= ab_pow6_re_r1;
|
|
ab_pow7_re0 <= ab_pow7_re_r1;
|
|
ab_pow8_re0 <= ab_pow8_re_r1;
|
|
ab_pow9_re0 <= ab_pow9_re_r1;
|
|
ab_powa_re0 <= ab_powa_re_r1;
|
|
ab_powb_re0 <= ab_powb_re_r1;
|
|
ab_powc_re0 <= ab_powc_re_r1;
|
|
ab_powd_re0 <= ab_powd_re_r1;
|
|
ab_powe_re0 <= ab_powe_re_r1;
|
|
ab_powf_re0 <= ab_powf_re_r1;
|
|
b_pow16_re0 <= b_pow16_re_r1;
|
|
a_im0 <= ao_im_r1 ;
|
|
b_im0 <= bo_im_r1 ;
|
|
ab_im0 <= ab_im_r1 ;
|
|
abb_im0 <= abb_im_r1 ;
|
|
ab_pow3_im0 <= ab_pow3_im_r1;
|
|
ab_pow4_im0 <= ab_pow4_im_r1;
|
|
ab_pow5_im0 <= ab_pow5_im_r1;
|
|
ab_pow6_im0 <= ab_pow6_im_r1;
|
|
ab_pow7_im0 <= ab_pow7_im_r1;
|
|
ab_pow8_im0 <= ab_pow8_im_r1;
|
|
ab_pow9_im0 <= ab_pow9_im_r1;
|
|
ab_powa_im0 <= ab_powa_im_r1;
|
|
ab_powb_im0 <= ab_powb_im_r1;
|
|
ab_powc_im0 <= ab_powc_im_r1;
|
|
ab_powd_im0 <= ab_powd_im_r1;
|
|
ab_powe_im0 <= ab_powe_im_r1;
|
|
ab_powf_im0 <= ab_powf_im_r1;
|
|
b_pow16_im0 <= b_pow16_im_r1;
|
|
end
|
|
vldi_r18[1]: begin
|
|
a_re1 <= ao_re_r1 ;
|
|
b_re1 <= bo_re_r1 ;
|
|
ab_re1 <= ab_re_r1 ;
|
|
abb_re1 <= abb_re_r1 ;
|
|
ab_pow3_re1 <= ab_pow3_re_r1;
|
|
ab_pow4_re1 <= ab_pow4_re_r1;
|
|
ab_pow5_re1 <= ab_pow5_re_r1;
|
|
ab_pow6_re1 <= ab_pow6_re_r1;
|
|
ab_pow7_re1 <= ab_pow7_re_r1;
|
|
ab_pow8_re1 <= ab_pow8_re_r1;
|
|
ab_pow9_re1 <= ab_pow9_re_r1;
|
|
ab_powa_re1 <= ab_powa_re_r1;
|
|
ab_powb_re1 <= ab_powb_re_r1;
|
|
ab_powc_re1 <= ab_powc_re_r1;
|
|
ab_powd_re1 <= ab_powd_re_r1;
|
|
ab_powe_re1 <= ab_powe_re_r1;
|
|
ab_powf_re1 <= ab_powf_re_r1;
|
|
b_pow16_re1 <= b_pow16_re_r1;
|
|
a_im1 <= ao_im_r1 ;
|
|
b_im1 <= bo_im_r1 ;
|
|
ab_im1 <= ab_im_r1 ;
|
|
abb_im1 <= abb_im_r1 ;
|
|
ab_pow3_im1 <= ab_pow3_im_r1;
|
|
ab_pow4_im1 <= ab_pow4_im_r1;
|
|
ab_pow5_im1 <= ab_pow5_im_r1;
|
|
ab_pow6_im1 <= ab_pow6_im_r1;
|
|
ab_pow7_im1 <= ab_pow7_im_r1;
|
|
ab_pow8_im1 <= ab_pow8_im_r1;
|
|
ab_pow9_im1 <= ab_pow9_im_r1;
|
|
ab_powa_im1 <= ab_powa_im_r1;
|
|
ab_powb_im1 <= ab_powb_im_r1;
|
|
ab_powc_im1 <= ab_powc_im_r1;
|
|
ab_powd_im1 <= ab_powd_im_r1;
|
|
ab_powe_im1 <= ab_powe_im_r1;
|
|
ab_powf_im1 <= ab_powf_im_r1;
|
|
b_pow16_im1 <= b_pow16_im_r1;
|
|
end
|
|
vldi_r18[2]: begin
|
|
a_re2 <= ao_re_r1 ;
|
|
b_re2 <= bo_re_r1 ;
|
|
ab_re2 <= ab_re_r1 ;
|
|
abb_re2 <= abb_re_r1 ;
|
|
ab_pow3_re2 <= ab_pow3_re_r1;
|
|
ab_pow4_re2 <= ab_pow4_re_r1;
|
|
ab_pow5_re2 <= ab_pow5_re_r1;
|
|
ab_pow6_re2 <= ab_pow6_re_r1;
|
|
ab_pow7_re2 <= ab_pow7_re_r1;
|
|
ab_pow8_re2 <= ab_pow8_re_r1;
|
|
ab_pow9_re2 <= ab_pow9_re_r1;
|
|
ab_powa_re2 <= ab_powa_re_r1;
|
|
ab_powb_re2 <= ab_powb_re_r1;
|
|
ab_powc_re2 <= ab_powc_re_r1;
|
|
ab_powd_re2 <= ab_powd_re_r1;
|
|
ab_powe_re2 <= ab_powe_re_r1;
|
|
ab_powf_re2 <= ab_powf_re_r1;
|
|
b_pow16_re2 <= b_pow16_re_r1;
|
|
a_im2 <= ao_im_r1 ;
|
|
b_im2 <= bo_im_r1 ;
|
|
ab_im2 <= ab_im_r1 ;
|
|
abb_im2 <= abb_im_r1 ;
|
|
ab_pow3_im2 <= ab_pow3_im_r1;
|
|
ab_pow4_im2 <= ab_pow4_im_r1;
|
|
ab_pow5_im2 <= ab_pow5_im_r1;
|
|
ab_pow6_im2 <= ab_pow6_im_r1;
|
|
ab_pow7_im2 <= ab_pow7_im_r1;
|
|
ab_pow8_im2 <= ab_pow8_im_r1;
|
|
ab_pow9_im2 <= ab_pow9_im_r1;
|
|
ab_powa_im2 <= ab_powa_im_r1;
|
|
ab_powb_im2 <= ab_powb_im_r1;
|
|
ab_powc_im2 <= ab_powc_im_r1;
|
|
ab_powd_im2 <= ab_powd_im_r1;
|
|
ab_powe_im2 <= ab_powe_im_r1;
|
|
ab_powf_im2 <= ab_powf_im_r1;
|
|
b_pow16_im2 <= b_pow16_im_r1;
|
|
end
|
|
vldi_r18[3]: begin
|
|
a_re3 <= ao_re_r1 ;
|
|
b_re3 <= bo_re_r1 ;
|
|
ab_re3 <= ab_re_r1 ;
|
|
abb_re3 <= abb_re_r1 ;
|
|
ab_pow3_re3 <= ab_pow3_re_r1;
|
|
ab_pow4_re3 <= ab_pow4_re_r1;
|
|
ab_pow5_re3 <= ab_pow5_re_r1;
|
|
ab_pow6_re3 <= ab_pow6_re_r1;
|
|
ab_pow7_re3 <= ab_pow7_re_r1;
|
|
ab_pow8_re3 <= ab_pow8_re_r1;
|
|
ab_pow9_re3 <= ab_pow9_re_r1;
|
|
ab_powa_re3 <= ab_powa_re_r1;
|
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ab_powb_re3 <= ab_powb_re_r1;
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ab_powc_re3 <= ab_powc_re_r1;
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ab_powd_re3 <= ab_powd_re_r1;
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ab_powe_re3 <= ab_powe_re_r1;
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ab_powf_re3 <= ab_powf_re_r1;
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b_pow16_re3 <= b_pow16_re_r1;
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a_im3 <= ao_im_r1 ;
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b_im3 <= bo_im_r1 ;
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ab_im3 <= ab_im_r1 ;
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abb_im3 <= abb_im_r1 ;
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ab_pow3_im3 <= ab_pow3_im_r1;
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ab_pow4_im3 <= ab_pow4_im_r1;
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ab_pow5_im3 <= ab_pow5_im_r1;
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ab_pow6_im3 <= ab_pow6_im_r1;
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ab_pow7_im3 <= ab_pow7_im_r1;
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ab_pow8_im3 <= ab_pow8_im_r1;
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ab_pow9_im3 <= ab_pow9_im_r1;
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ab_powa_im3 <= ab_powa_im_r1;
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ab_powb_im3 <= ab_powb_im_r1;
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ab_powc_im3 <= ab_powc_im_r1;
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ab_powd_im3 <= ab_powd_im_r1;
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ab_powe_im3 <= ab_powe_im_r1;
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ab_powf_im3 <= ab_powf_im_r1;
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b_pow16_im3 <= b_pow16_im_r1;
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end
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// default: begin
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// ao_re[0] <= 'h0;
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// ab_re[0] <= 'h0;
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// abb_re[0] <= 'h0;
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// ab_pow3_re[0] <= 'h0;
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// ab_pow4_re[0] <= 'h0;
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// ab_pow5_re[0] <= 'h0;
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// ab_pow6_re[0] <= 'h0;
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// ab_pow7_re[0] <= 'h0;
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// b_pow8_re[0] <= 'h0;
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// end
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endcase
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end
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end
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endmodule
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