40 lines
785 B
Verilog
40 lines
785 B
Verilog
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module mult_real #(
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parameter integer A_width = 8
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,parameter integer C_width = 8
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,parameter integer o_width = 31//division
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)
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(
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input rstn
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,input clk
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,input en
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,input signed [A_width-1 :0] din
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,input signed [C_width-1 :0] coef
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,output signed [o_width-1 :0] dout
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);
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wire signed [A_width+C_width-1:0] ac;
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wire signed [o_width-1 :0] Re_trunc;
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DW02_mult #(A_width,C_width) inst_c1 (
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.A (din ),
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.B (coef ),
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.TC (1'b1 ),
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.PRODUCT (ac )
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);
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trunc #(
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.diw (A_width+C_width )
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,.msb (A_width+C_width-2 )
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,.lsb (A_width+C_width-o_width-1 )
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) u_round1 (clk, rstn, en, ac, Re_trunc);
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assign dout = Re_trunc;
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endmodule
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