thfu 6908587dae v01-enable of clk_div2;8pin to 4pin;valid I/O		2024-11-25 23:05:43 +08:00
..
clk_gen.v	add 8 interpolation	2024-10-08 11:24:32 +08:00
tb_diff.v	add 8 interpolation	2024-10-08 11:24:32 +08:00
tb_iir.v	add 8 interpolation	2024-10-08 11:24:32 +08:00
tb_iir.v.bak	add 8 interpolation	2024-10-08 11:24:32 +08:00
tb_mean2.v	add 8 interpolation	2024-10-08 11:24:32 +08:00
tb_mean4.v	add 8 interpolation	2024-10-08 11:24:32 +08:00
tb_mean4_top.v	add 8 interpolation	2024-10-08 11:24:32 +08:00
tb_mean8_top.v	modify relevant .v file and .m file to verify the accuracy of rtl code	2024-10-17 17:29:11 +08:00
tb_top.v.bak	add 8 interpolation	2024-10-08 11:24:32 +08:00
tb_z_dsp.v	Modify enable signal as clk divided by 2	2024-11-04 19:03:02 +08:00
tb_z_dsp_en_Test.v	v01-enable of clk_div2;8pin to 4pin;valid I/O	2024-11-25 23:05:43 +08:00