unknown 9dcfcd4028 v01-.v files convert reg to wire;.m files include diff and sqt both less than 1e-4		2024-11-26 20:38:29 +08:00
..
model	v01-add round module;intp8 and mult_C using round;Modify the directory structure	2024-11-26 13:34:17 +08:00
nco	modify relevant .v file and .m file to verify the accuracy of rtl code	2024-10-17 17:29:11 +08:00
z_dsp	v01-.v files convert reg to wire;.m files include diff and sqt both less than 1e-4	2024-11-26 20:38:29 +08:00
z_dsp_en_Test.v	v01-enable of clk_div2;8pin to 4pin;valid I/O	2024-11-25 23:05:43 +08:00