90 lines
2.8 KiB
Verilog
90 lines
2.8 KiB
Verilog
//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : Z_dsp.v
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// Department :
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// Author : thfu
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.2 2024-10-09 thfu to fit the addition of 8 interpolation
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module rate_adapter
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(
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input rstn
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,input clk
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,input en
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,input vldi
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,input signed [15:0] din0
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,input signed [15:0] din1
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,input signed [15:0] din2
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,input signed [15:0] din3
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,input signed [15:0] din4
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,input signed [15:0] din5
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,input signed [15:0] din6
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,input signed [15:0] din7
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,output signed [15:0] dout0
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,output signed [15:0] dout1
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,output signed [15:0] dout2
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,output signed [15:0] dout3
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,output reg vldo
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);
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reg signed [15:0] doutf_0;
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reg signed [15:0] doutf_1;
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reg signed [15:0] doutf_2;
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reg signed [15:0] doutf_3;
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always@(posedge clk or negedge rstn)
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if(!rstn) begin
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doutf_0 <= 0;
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doutf_1 <= 0;
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doutf_2 <= 0;
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doutf_3 <= 0;
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end
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else if(!en) begin
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doutf_0 <= din0;
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doutf_1 <= din1;
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doutf_2 <= din2;
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doutf_3 <= din3;
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end
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else begin
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doutf_0 <= din4;
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doutf_1 <= din5;
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doutf_2 <= din6;
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doutf_3 <= din7;
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end
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assign dout0 = doutf_0;
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assign dout1 = doutf_1;
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assign dout2 = doutf_2;
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assign dout3 = doutf_3;
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syncer #(1, 1) sync_diff7_syncer (clk, rstn, vldi, vldo);
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endmodule
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