318 lines
9.9 KiB
Verilog
318 lines
9.9 KiB
Verilog
module TB();
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initial
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begin
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$fsdbDumpfile("TB.fsdb");
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$fsdbDumpvars(0, TB);
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end
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reg rstn;
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reg [31:0] a0_re;
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reg [31:0] a0_im;
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reg [31:0] ab0_re;
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reg [31:0] ab0_im;
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reg [31:0] a1_re;
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reg [31:0] a1_im;
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reg [31:0] ab1_re;
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reg [31:0] ab1_im;
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reg [31:0] a2_re;
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reg [31:0] a2_im;
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reg [31:0] ab2_re;
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reg [31:0] ab2_im;
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reg [31:0] a3_re;
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reg [31:0] a3_im;
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reg [31:0] ab3_re;
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reg [31:0] ab3_im;
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reg [31:0] a4_re;
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reg [31:0] a4_im;
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reg [31:0] ab4_re;
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reg [31:0] ab4_im;
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reg [31:0] a5_re;
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reg [31:0] a5_im;
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reg [31:0] ab5_re;
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reg [31:0] ab5_im;
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reg [31:0] bb0_re;
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reg [31:0] bb1_re;
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reg [31:0] bb2_re;
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reg [31:0] bb3_re;
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reg [31:0] bb4_re;
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reg [31:0] bb5_re;
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reg [31:0] bb0_im;
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reg [31:0] bb1_im;
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reg [31:0] bb2_im;
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reg [31:0] bb3_im;
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reg [31:0] bb4_im;
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reg [31:0] bb5_im;
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reg [47:0] fcw;
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reg [21:0] cnt;
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reg [15:0] din_rect;
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reg [15:0] din_cos;
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reg [15:0] iir_in;
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reg [1 :0] source_mode;
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wire [15:0] cos;
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wire [15:0] sin;
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reg clk;
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reg clk_div2;
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reg clk_div4;
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initial
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begin
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#0;
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rstn = 1'b0;
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clk = 1'b0;
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clk_div2 = 1'b0;
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clk_div4 = 1'b0;
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a0_re = 32'd55007237 ;
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a1_re = 1*32'd32690030 ;
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a2_re = 1*32'd429516;
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a3_re = 32'd0;
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a4_re = 32'd0;
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a5_re = 32'd0;
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a0_im = 32'd0;
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a1_im = 32'd0;
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a2_im = 32'd0;
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a3_im = 32'd0;
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a4_im = 32'd0;
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a5_im = 32'd0;
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ab0_re = 32'd54894517;
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ab1_re = 1*32'd32664510;
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ab2_re = 1*32'd429381;
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ab3_re = 32'd0;
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ab4_re = 32'd0;
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ab5_re = 32'd0;
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ab0_im = 32'd0;
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ab1_im = 32'd0;
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ab2_im = 32'd0;
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ab3_im = 32'd0;
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ab4_im = 32'd0;
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ab5_im = 32'd0;
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bb0_re = 32'd2138691506;
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bb1_re = 32'd2144132133;
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bb2_re = 32'd2146141622;
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bb3_re = 32'd0;
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bb4_re = 32'd0;
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bb5_re = 32'd0;
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bb0_im = 32'd0;
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bb1_im = 32'd0;
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bb2_im = 32'd0;
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bb3_im = 32'd0;
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bb4_im = 32'd0;
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bb5_im = 32'd0;
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fcw = 48'h0840_0000_0000;
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din_rect = 16'd0;
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din_cos = 16'd0;
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#300;
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rstn = 1'b1;
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#16600300;
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// din_rect = 16'd30000;
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// en = 1'b1;
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#6400;
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#64000;
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// din_rect = 16'd0;
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end
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always #200 clk = ~clk;
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always #400 clk_div2 = ~clk_div2;
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always #800 clk_div4 = ~clk_div4;
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always@(posedge clk_div2 or negedge rstn)
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if(!rstn)
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cnt <= 22'd0;
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else
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cnt <= cnt + 22'd1;
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initial
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begin
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wait(cnt[16]==1'b1)
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$finish(0);
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end
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always@(posedge clk or negedge rstn)
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if(!rstn)
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din_rect <= 22'd0;
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else if(cnt >= 100 && cnt <=10100)
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begin
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din_rect <= 16'd30000;
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end
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else
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begin
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din_rect <= 16'd0;
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end
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always@(posedge clk or negedge rstn)
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if(!rstn)
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begin
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iir_in <= 16'd0;
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end
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else
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assign source_mode = 2'b01;
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always @(*)
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case(source_mode)
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2'b01 : iir_in = din_rect;
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endcase
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wire [1:0] intp_mode;
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assign intp_mode = 2'b10;
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wire [1:0] dac_mode_sel;
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assign dac_mode_sel = 2'b00;
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wire tc_bypass;
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wire vldo;
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assign tc_bypass = 1'b0;
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reg en;
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always @(posedge clk or negedge rstn)begin
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if(rstn==1'b0)begin
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en <= 0;
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end
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else begin
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en <= ~en;
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end
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end
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wire [15:0] dout_p0;
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wire [15:0] dout_p1;
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wire [15:0] dout_p2;
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wire [15:0] dout_p3;
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z_dsp inst_z_dsp_en
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(
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.clk (clk ),
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.en (en ),
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.rstn (rstn ),
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.tc_bypass (tc_bypass ),
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.vldi (iir_in[14] ),
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.dac_mode_sel (dac_mode_sel ),
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.intp_mode (intp_mode ),
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.din (iir_in ),
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.a0_re (a0_re ),
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.a0_im (a0_im ),
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.ab0_re (ab0_re ),
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.ab0_im (ab0_im ),
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.bb0_re (bb0_re ),
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.bb0_im (bb0_im ),
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.a1_re (a1_re ),
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.a1_im (a1_im ),
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.ab1_re (ab1_re ),
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.ab1_im (ab1_im ),
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.bb1_re (bb1_re ),
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.bb1_im (bb1_im ),
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.a2_re (a2_re ),
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.a2_im (a2_im ),
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.ab2_re (ab2_re ),
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.ab2_im (ab2_im ),
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.bb2_re (bb2_re ),
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.bb2_im (bb2_im ),
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.a3_re (a3_re ),
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.a3_im (a3_im ),
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.ab3_re (ab3_re ),
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.ab3_im (ab3_im ),
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.bb3_re (bb3_re ),
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.bb3_im (bb3_im ),
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.a4_re (a4_re ),
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.a4_im (a4_im ),
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.ab4_re (ab4_re ),
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.ab4_im (ab4_im ),
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.bb4_re (bb4_re ),
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.bb4_im (bb4_im ),
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.a5_re (a5_re ),
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.a5_im (a5_im ),
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.ab5_re (ab5_re ),
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.ab5_im (ab5_im ),
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.bb5_re (bb5_re ),
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.bb5_im (bb5_im ),
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.dout0 (dout_p0 ),
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.dout1 (dout_p1 ),
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.dout2 (dout_p2 ),
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.dout3 (dout_p3 ),
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.vldo (vldo )
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);
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wire [15:0] dout_clkl_p0;
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wire [15:0] dout_clkl_p1;
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wire [15:0] dout_clkl_p2;
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wire [15:0] dout_clkl_p3;
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wire [15:0] dout_clkl_p4;
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wire [15:0] dout_clkl_p5;
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wire [15:0] dout_clkl_p6;
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wire [15:0] dout_clkl_p7;
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integer signed In_fid;
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integer signed OrgOut_fid;
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integer signed dout0_fid;
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integer signed dout1_fid;
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integer signed dout2_fid;
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integer signed dout3_fid;
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initial begin
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#0;
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In_fid = $fopen("./in.dat") ;
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OrgOut_fid = $fopen("./OrgOut.dat");
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dout0_fid = $fopen("./dout0.dat");
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dout1_fid = $fopen("./dout1.dat");
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dout2_fid = $fopen("./dout2.dat");
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dout3_fid = $fopen("./dout3.dat");
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end
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always@(posedge clk)
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if(cnt >= 90) begin
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$fwrite(In_fid, "%d\n",$signed(TB.inst_z_dsp_en.inst_TailCorr_top.din));
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$fwrite(OrgOut_fid,"%d\n",$signed(TB.inst_z_dsp_en.inst_TailCorr_top.Ysum));
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end
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always@(posedge clk)
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if(cnt >= 90 )
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begin
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$fwrite(dout0_fid,"%d\n",$signed(dout_p0));
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$fwrite(dout1_fid,"%d\n",$signed(dout_p1));
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$fwrite(dout2_fid,"%d\n",$signed(dout_p2));
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$fwrite(dout3_fid,"%d\n",$signed(dout_p3));
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end
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integer signed doutp0_fid;
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integer signed doutp1_fid;
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initial begin
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#0;
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doutp0_fid = $fopen("./doutp0.dat");
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doutp1_fid = $fopen("./doutp1.dat");
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end
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always@(posedge clk)
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if(cnt >= 90 && en)
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begin
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$fwrite(doutp0_fid,"%d\n",$signed(TB.inst_z_dsp_en.inst_TailCorr_top.dout_p0));
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$fwrite(doutp1_fid,"%d\n",$signed(TB.inst_z_dsp_en.inst_TailCorr_top.dout_p1));
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end
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endmodule
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