63 lines
1.1 KiB
Verilog
Executable File
63 lines
1.1 KiB
Verilog
Executable File
module P_NCO(
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clk,
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rstn,
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clr,
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clr_acc,
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pha,
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s1,
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s2,
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s3,
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s1_o,
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s2_o,
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s3_o,
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fcw,
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cos,
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sin
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);
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input clk;
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input rstn;
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input clr;
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input clr_acc;
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input [15:0] pha;
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input [15:0] s1;
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input [15:0] s2;
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input [15:0] s3;
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output [15:0] s1_o;
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output [15:0] s2_o;
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output [15:0] s3_o;
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output [15:0] cos;
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output [15:0] sin;
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input [47:0] fcw;
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reg [15:0] pha_r;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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pha_r <= 16'd0;
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else
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pha_r <= pha;
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wire [18:0] pha0;
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PIPE3_ACC_48BIT inst_pipe(.clk(clk),.rstn(rstn),.in(fcw),.clr(clr_acc),.ptw(pha),.s_o_1(s1_o),.s_o_2(s2_o),.s_o_3(s3_o),.s_i_1(s1),.s_i_2(s2),.s_i_3(s3),.out(pha0));
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PH2AMP inst_ph2amp_0(
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.clk(clk) ,
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.rstn(rstn) ,
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.pha_map(pha0) ,
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.sin_o(sin) ,
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.cos_o(cos)
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);
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endmodule
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