169 lines
4.5 KiB
Verilog
169 lines
4.5 KiB
Verilog
module TB();
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parameter data_in_width = 16;
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parameter max_coef_width = 32;
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parameter frac_data_out_width = 20;//X for in,5
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parameter frac_coef_width = 31;//division
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parameter feedback_width = 36;
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parameter data_out_width = 36;
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parameter saturation_mode = 0;
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parameter out_reg = 1;
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initial
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begin
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$fsdbDumpfile("TB.fsdb");
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$fsdbDumpvars(0, TB);
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end
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reg clk;
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reg rstn;
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reg [15:0] din_im;
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reg [36:0] a;
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reg [36:0] b;
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reg [20:0] c;
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reg [20:0] d;
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reg [47:0] fcw;
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reg [21:0] cnt;
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reg [15:0] din_imp;
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reg [15:0] din_rect;
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reg [15:0] din_cos;
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reg [15:0] diff_in;
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reg en;
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wire [1 :0] source_mode;
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wire [15 :0] iir_in;
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wire [15:0] cos;
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wire [15:0] sin;
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wire [35:0] dout_p0;
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initial
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begin
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#0;
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rstn = 1'b0;
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clk = 1'b0;
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din_im = 16'd0;
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a = 37'd1757225200;
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b = 37'd0;
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c = -21'd1042856;
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d = 21'd0;
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fcw = 48'h0840_0000_0000;
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din_imp = 16'd0;
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din_rect = 16'd0;
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din_cos = 16'd0;
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#3600;
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en = 1'b1;
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#3800;
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rstn = 1'b1;
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din_imp = 16'd32767;
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din_rect = 8'd1;
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#400;
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din_imp = 16'd0;
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#12000;
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din_rect = 16'd0;
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end
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always #200 clk = ~clk;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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cnt <= 22'd0;
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else
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cnt <= cnt + 22'd1;
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initial
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begin
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wait(cnt[16]==1'b1)
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$finish(0);
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end
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always@(posedge clk or negedge rstn)
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if(!rstn)
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begin
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din_cos <= 16'd0;
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diff_in <= 16'd0;
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end
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else
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din_cos <= cos;
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assign source_mode = 2'b00;
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always @(*)
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case(source_mode)
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2'b00 : diff_in = din_imp;
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2'b01 : diff_in = din_rect;
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2'b10 : diff_in = din_cos;
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endcase
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NCO inst_nco_0(
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.clk (clk ),
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.rstn (rstn ),
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.phase_manual_clr (1'b0 ),
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.phase_auto_clr (1'b0 ),
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.fcw (fcw ),
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.pha (16'd0 ),
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.cos (cos ),
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.sin (sin )
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);
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DW_iir_dc
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#(
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.data_in_width (data_in_width ),
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.data_out_width (data_out_width ),
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.frac_data_out_width (frac_data_out_width),
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.feedback_width (feedback_width ),
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.max_coef_width (max_coef_width ),
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.frac_coef_width (frac_coef_width ),
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.saturation_mode (saturation_mode ),
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.out_reg (out_reg )
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)
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inst_iir_0
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(
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.clk (clk ),
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.rst_n (rstn ),
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.init_n (rstn ),
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.enable (en ),
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.A1_coef (32'd2143083069 ),//Den
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.A2_coef ('h0 ),
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.B0_coef (32'd55007236 ),//Num
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.B1_coef ('h0 ),
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.B2_coef ('h0 ),
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.data_in (diff_in ),
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.data_out (dout_p0 ),
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.saturation ( )
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);
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integer signed In_fid;
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integer signed Out_fid;
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initial begin
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#0;
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In_fid = $fopen("./in");
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Out_fid = $fopen("./out");
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end
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always@(posedge clk)
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$fwrite(In_fid,"%d\n",{{~{diff_in[15]}},diff_in[14:0]});
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always@(posedge clk)
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$fwrite(Out_fid,"%d\n",{{~{dout_p0[35]}},dout_p0[34:0]});
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endmodule
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