67 lines
1.4 KiB
Verilog
67 lines
1.4 KiB
Verilog
module mult_x #(
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parameter integer A_width = 8
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,parameter integer C_width = 8
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,parameter integer D_width = 8
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,parameter integer o_width = 31//division
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)
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(
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clk,
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rstn,
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en,
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a,
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c,
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d,
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Re,
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Im
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);
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input rstn;
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input clk;
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input en;
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input signed [A_width-1 :0] a;
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input signed [C_width-1 :0] c;
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input signed [D_width-1 :0] d;
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output signed [o_width-1 :0] Re;
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output signed [o_width-1 :0] Im;
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wire signed [A_width+C_width-1:0] ac;
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wire signed [A_width+D_width-1:0] ad;
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wire signed [o_width-1 :0] Re_trunc;
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wire signed [o_width-1 :0] Im_trunc;
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DW02_mult #(A_width,C_width) inst_c1( .A (a ),
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.B (c ),
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.TC (1'b1 ),
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.PRODUCT (ac )
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);
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DW02_mult #(A_width,D_width) inst_c3( .A (a ),
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.B (d ),
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.TC (1'b1 ),
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.PRODUCT (ad )
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);
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trunc #(
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.diw (A_width+C_width )
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,.msb (A_width+C_width-2 )
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,.lsb (A_width+C_width-o_width-1 )
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) u_round1 (clk, rstn, en, ac, Re_trunc);
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trunc #(
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.diw (A_width+D_width )
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,.msb (A_width+D_width-2 )
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,.lsb (A_width+D_width-o_width-1 )
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) u_round2 (clk, rstn, en, ad, Im_trunc);
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// Since this is complex multiplication, the output bit width needs to be increased by one compared to the input.
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assign Re = Re_trunc;
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assign Im = Im_trunc;
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endmodule
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