281 lines
7.4 KiB
Verilog
281 lines
7.4 KiB
Verilog
`timescale 1 ns/1 ns
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module TB();
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reg [1 :0] source_mode;
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initial
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begin
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$fsdbDumpfile("TB.fsdb");
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$fsdbDumpvars(0, TB);
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$fsdbDumpMDA();
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// $srandom(417492050);
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source_mode = 2'd2; //1 for rect;2 for random;3 from matlab
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end
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reg rstn;
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reg [15:0] din_rect;
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reg [ 5:0] vldi_coef;
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reg vldi_data;
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parameter CYCLE = 20;
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reg clk;
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initial begin
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clk = 0;
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forever
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#(CYCLE/2)
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clk=~clk;
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end
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reg signed [31:0] a_re [5:0];
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reg signed [31:0] b_re [5:0];
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initial begin
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rstn = 0;
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vldi_data <= 0;
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vldi_coef <= 0;
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din_rect = 16'd0;
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a_re[3] <= 0;
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b_re[3] <= 0;
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a_re[4] <= 0;
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b_re[4] <= 0;
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a_re[5] <= 0;
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b_re[5] <= 0;
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repeat(3) @(posedge clk);
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vldi_coef[0] <= 1;
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rstn = 1;
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a_re[0] <= 55007237;
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b_re[0] <= 2143083068;
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@(posedge clk);
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vldi_coef[0] <= 0;
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a_re[0] <= 0;
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b_re[0] <= 0;
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repeat(8) @(posedge clk);
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vldi_coef[1] <= 1;
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rstn = 1;
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a_re[1] <= 32690030;
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b_re[1] <= 2145807236;
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@(posedge clk);
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vldi_coef[1] <= 0;
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a_re[1] <= 0;
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b_re[1] <= 0;
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repeat(8) @(posedge clk);
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vldi_coef[2] <= 1;
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rstn = 1;
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a_re[2] <= 429516;
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b_re[2] <= 2146812530;
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@(posedge clk);
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vldi_coef[2] <= 0;
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a_re[2] <= 0;
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b_re[2] <= 0;
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repeat(108) @(posedge clk);
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vldi_data <= 1;
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// repeat(10000) @(posedge clk);
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// vldi_data <= 0;
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end
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reg [21:0] cnt;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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cnt <= 22'd0;
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else
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cnt <= cnt + 22'd1;
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initial
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begin
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wait(cnt[16]==1'b1)
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$finish(0);
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end
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reg vldi_data_r1;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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vldi_data_r1 <= 1'b0;
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else
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begin
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vldi_data_r1 <= vldi_data;
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end
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always@(posedge clk or negedge rstn)
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if(!rstn)
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din_rect <= 22'd0;
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else if(vldi_data)
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begin
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din_rect <= 16'd30000;
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end
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else
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begin
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din_rect <= 16'd0;
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end
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reg signed [15:0] random_in [0:3];
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always @(posedge clk or negedge rstn) begin
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if (!rstn) begin
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for (int i = 0; i < 4; i = i + 1) begin
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random_in[i] <= 16'd0;
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end
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end
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else if (vldi_data) begin
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for (int i = 0; i < 4; i = i + 1) begin
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random_in[i] <= $urandom % 30000;
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end
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end
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else begin
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for (int i = 0; i < 4; i = i + 1) begin
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random_in[i] <= 16'd0;
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end
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end
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end
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integer file[3:0];
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reg [15:0] data[3:0];
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integer status[3:0];
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reg [15:0] reg_array[3:0];
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initial begin
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if(source_mode == 3) begin
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string filenames[0:3] = {"in0_matlab.dat", "in1_matlab.dat", "in2_matlab.dat", "in3_matlab.dat"};
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for (int i = 0; i < 4; i = i + 1) begin
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file[i] = $fopen(filenames[i], "r");
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if (file[i] == 0) begin
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$display("Failed to open file: %s", filenames[i]);
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$finish;
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end
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end
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end
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end
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always @(posedge clk or negedge rstn) begin
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if (!rstn) begin
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for (int i = 0; i < 4; i = i + 1) begin
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reg_array[i] <= 16'd0;
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end
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end else if(vldi_data && source_mode == 3) begin
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for (int i = 0; i < 4; i = i + 1) begin
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status[i] = $fscanf(file[i], "%d\n", data[i]);
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if (status[i] == 1 ) begin
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reg_array[i] <= data[i];
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end
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else begin
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reg_array[i] <= 16'd0;
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vldi_data <= 0;
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end
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end
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end
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end
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reg signed [15:0] iir_in[3:0];
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always @(*)
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case(source_mode)
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2'b01 : begin
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for (int i = 0; i < 4; i = i + 1) begin
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iir_in[i] = din_rect;
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end
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end
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2'b10 : begin
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for (int i = 0; i < 4; i = i + 1) begin
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iir_in[i] = random_in[i];
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end
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end
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2'b11 : begin
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for (int i = 0; i < 4; i = i + 1) begin
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iir_in[i] = reg_array[i];
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end
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end
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endcase
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wire [1:0] intp_mode;
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assign intp_mode = 2'b10;
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wire [1:0] dac_mode_sel;
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assign dac_mode_sel = 2'b00;
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wire tc_bypass;
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wire vldo;
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assign tc_bypass = 1'b0;
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reg en;
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always @(posedge clk or negedge rstn)begin
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if(rstn==1'b0)begin
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en <= 1;
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end
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else begin
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en <= ~en;
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end
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end
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wire signed [15:0] dout_p[7:0];
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z_dsp inst_z_dsp(
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.rstn (rstn ),
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.clk (clk ),
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.en (en ),
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// .tc_bypass (tc_bypass ),
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.vldi_coef (vldi_coef ),
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.vldi_data (vldi_data_r1 ),
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// .intp_mode (intp_mode ),
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// .dac_mode_sel (dac_mode_sel ),
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.din0 (iir_in[0] ),
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.din1 (iir_in[1] ),
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.din2 (iir_in[2] ),
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.din3 (iir_in[3] ),
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.a0_re (a_re[0] ),
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.b0_re (b_re[0] ),
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.a1_re (a_re[1] ),
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.b1_re (b_re[1] ),
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.a2_re (a_re[2] ),
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.b2_re (b_re[2] ),
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.a3_re (a_re[3] ),
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.b3_re (b_re[3] ),
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.a4_re (a_re[4] ),
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.b4_re (b_re[4] ),
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.a5_re (a_re[5] ),
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.b5_re (b_re[5] ),
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.dout0 (dout_p[0] ),
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.dout1 (dout_p[1] ),
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.dout2 (dout_p[2] ),
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.dout3 (dout_p[3] ),
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.vldo ( vldo )
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);
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integer signed In_fid[0:3];
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integer signed dout_fid[0:7];
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string filenames_in[0:3] = {"in0.dat", "in1.dat", "in2.dat", "in3.dat"};
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string filenames_dout[0:7] = {"dout0.dat", "dout1.dat", "dout2.dat", "dout3.dat", "dout4.dat", "dout5.dat", "dout6.dat", "dout7.dat"};
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initial begin
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#0;
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for (int i = 0; i < 4; i = i + 1) begin
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In_fid[i] = $fopen(filenames_in[i]);
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end
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for (int i = 0; i < 4; i = i + 1) begin
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dout_fid[i] = $fopen(filenames_dout[i]);
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end
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end
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always @(posedge clk) begin
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if (vldi_data_r1) begin
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for (int i = 0; i < 4; i = i + 1) begin
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$fwrite(In_fid[i], "%d\n", $signed(iir_in[i]));
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end
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end
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end
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always @(posedge clk) begin
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if (vldo) begin
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for (int i = 0; i < 4; i = i + 1) begin
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$fwrite(dout_fid[i], "%d\n", $signed(dout_p[i]));
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end
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end
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end
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endmodule
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