797 lines
30 KiB
Verilog
797 lines
30 KiB
Verilog
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module TailCorr_top #(
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parameter temp_var_width = 22
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)
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(
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input rstn
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,input clk
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,input en
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,input vldi
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,input signed [15:0] din0
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,input signed [15:0] din1
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,input signed [15:0] din2
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,input signed [15:0] din3
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,input signed [31:0] a_re0
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,input signed [31:0] b_re0
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,input signed [31:0] ab_re0
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,input signed [31:0] abb_re0
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,input signed [31:0] ab_pow3_re0
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,input signed [31:0] ab_pow4_re0
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,input signed [31:0] ab_pow5_re0
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,input signed [31:0] ab_pow6_re0
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,input signed [31:0] ab_pow7_re0
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,input signed [31:0] b_pow8_re0
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,input signed [31:0] a_re1
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,input signed [31:0] b_re1
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,input signed [31:0] ab_re1
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,input signed [31:0] abb_re1
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,input signed [31:0] ab_pow3_re1
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,input signed [31:0] ab_pow4_re1
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,input signed [31:0] ab_pow5_re1
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,input signed [31:0] ab_pow6_re1
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,input signed [31:0] ab_pow7_re1
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,input signed [31:0] b_pow8_re1
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,input signed [31:0] a_re2
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,input signed [31:0] b_re2
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,input signed [31:0] ab_re2
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,input signed [31:0] abb_re2
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,input signed [31:0] ab_pow3_re2
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,input signed [31:0] ab_pow4_re2
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,input signed [31:0] ab_pow5_re2
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,input signed [31:0] ab_pow6_re2
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,input signed [31:0] ab_pow7_re2
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,input signed [31:0] b_pow8_re2
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,input signed [31:0] a_re3
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,input signed [31:0] b_re3
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,input signed [31:0] ab_re3
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,input signed [31:0] abb_re3
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,input signed [31:0] ab_pow3_re3
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,input signed [31:0] ab_pow4_re3
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,input signed [31:0] ab_pow5_re3
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,input signed [31:0] ab_pow6_re3
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,input signed [31:0] ab_pow7_re3
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,input signed [31:0] b_pow8_re3
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,input signed [31:0] a_re4
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,input signed [31:0] b_re4
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,input signed [31:0] ab_re4
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,input signed [31:0] abb_re4
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,input signed [31:0] ab_pow3_re4
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,input signed [31:0] ab_pow4_re4
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,input signed [31:0] ab_pow5_re4
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,input signed [31:0] ab_pow6_re4
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,input signed [31:0] ab_pow7_re4
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,input signed [31:0] b_pow8_re4
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,input signed [31:0] a_re5
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,input signed [31:0] b_re5
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,input signed [31:0] ab_re5
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,input signed [31:0] abb_re5
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,input signed [31:0] ab_pow3_re5
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,input signed [31:0] ab_pow4_re5
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,input signed [31:0] ab_pow5_re5
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,input signed [31:0] ab_pow6_re5
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,input signed [31:0] ab_pow7_re5
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,input signed [31:0] b_pow8_re5
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,output signed [15:0] dout_p0
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,output signed [15:0] dout_p1
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,output signed [15:0] dout_p2
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,output signed [15:0] dout_p3
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,output signed [15:0] dout_p4
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,output signed [15:0] dout_p5
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,output signed [15:0] dout_p6
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,output signed [15:0] dout_p7
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,output vldo
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);
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wire signed [15:0] din_p0;
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wire signed [15:0] din_p1;
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wire signed [15:0] din_p2;
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wire signed [15:0] din_p3;
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wire signed [15:0] din_p4;
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wire signed [15:0] din_p5;
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wire signed [15:0] din_p6;
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wire signed [15:0] din_p7;
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wire signed [15:0] IIRin_p0; // iirin_x(8n+9)
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wire signed [15:0] IIRin_p1; // iirin_x(8n+10)
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wire signed [15:0] IIRin_p2; // iirin_x(8n+11)
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wire signed [15:0] IIRin_p3; // iirin_x(8n+12)
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wire signed [15:0] IIRin_p4; // iirin_x(8n+13)
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wire signed [15:0] IIRin_p5; // iirin_x(8n+14)
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wire signed [15:0] IIRin_p6; // iirin_x(8n+15)
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wire signed [15:0] IIRin_p7; // iirin_x(8n+16)
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wire signed [temp_var_width-1:0] IIRout_p0 [5:0]; // iirout_y(8n-8)
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wire signed [temp_var_width-1:0] IIRout_p1 [5:0]; // iirout_y(8n-23)
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wire signed [temp_var_width-1:0] IIRout_p2 [5:0]; // iirout_y(8n-38)
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wire signed [temp_var_width-1:0] IIRout_p3 [5:0]; // iirout_y(8n-53)
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wire signed [temp_var_width-1:0] IIRout_p4 [5:0]; // iirout_y(8n-68)
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wire signed [temp_var_width-1:0] IIRout_p5 [5:0]; // iirout_y(8n-83)
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wire signed [temp_var_width-1:0] IIRout_p6 [5:0]; // iirout_y(8n-98)
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wire signed [temp_var_width-1:0] IIRout_p7 [5:0]; // iirout_y(8n-113)
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wire signed [temp_var_width+2:0] sum_IIRout_p0;
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wire signed [temp_var_width+2:0] sum_IIRout_p1;
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wire signed [temp_var_width+2:0] sum_IIRout_p2;
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wire signed [temp_var_width+2:0] sum_IIRout_p3;
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wire signed [temp_var_width+2:0] sum_IIRout_p4;
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wire signed [temp_var_width+2:0] sum_IIRout_p5;
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wire signed [temp_var_width+2:0] sum_IIRout_p6;
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wire signed [temp_var_width+2:0] sum_IIRout_p7;
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reg signed [15:0] din_p0_r [16:0];
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reg signed [15:0] din_p1_r [16:0];
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reg signed [15:0] din_p2_r [16:0];
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reg signed [15:0] din_p3_r [16:0];
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reg signed [15:0] din_p4_r [16:0];
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reg signed [15:0] din_p5_r [16:0];
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reg signed [15:0] din_p6_r [16:0];
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reg signed [15:0] din_p7_r [16:0];
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reg signed [15:0] IIRin_p0_r [1 :0]; // iirin_x(8n-7)
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reg signed [15:0] IIRin_p1_r [3 :0]; // iirin_x(8n-22)
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reg signed [15:0] IIRin_p2_r [5 :0]; // iirin_x(8n-37)
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reg signed [15:0] IIRin_p3_r [7 :0]; // iirin_x(8n-53)
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reg signed [15:0] IIRin_p4_r [9 :0]; // iirin_x(8n-67)
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reg signed [15:0] IIRin_p5_r [11:0]; // iirin_x(8n-82)
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reg signed [15:0] IIRin_p6_r [13:0]; // iirin_x(8n-97)
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reg signed [temp_var_width+2:0] sum_IIRout_p0_r [12:0];
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reg signed [temp_var_width+2:0] sum_IIRout_p1_r [11:0];
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reg signed [temp_var_width+2:0] sum_IIRout_p2_r [9 :0];
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reg signed [temp_var_width+2:0] sum_IIRout_p3_r [7 :0];
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reg signed [temp_var_width+2:0] sum_IIRout_p4_r [5 :0];
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reg signed [temp_var_width+2:0] sum_IIRout_p5_r [3 :0];
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reg signed [temp_var_width+2:0] sum_IIRout_p6_r [1 :0];
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wire signed [temp_var_width+2:0] dout_p0_r0;
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wire signed [temp_var_width+2:0] dout_p1_r0;
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wire signed [temp_var_width+2:0] dout_p2_r0;
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wire signed [temp_var_width+2:0] dout_p3_r0;
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wire signed [temp_var_width+2:0] dout_p4_r0;
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wire signed [temp_var_width+2:0] dout_p5_r0;
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wire signed [temp_var_width+2:0] dout_p6_r0;
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wire signed [temp_var_width+2:0] dout_p7_r0;
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wire vldo_diff;
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diff_p inst_diff_p (
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.rstn (rstn),
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.clk (clk ),
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.en (en ),
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.vldi (vldi),
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.din0 (din0),
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.din1 (din1),
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.din2 (din2),
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.din3 (din3),
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.vldo (vldo_diff),
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.dout_p0 (din_p0),
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.dout_p1 (din_p1),
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.dout_p2 (din_p2),
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.dout_p3 (din_p3),
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.dout_p4 (din_p4),
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.dout_p5 (din_p5),
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.dout_p6 (din_p6),
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.dout_p7 (din_p7),
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.diff_p0 (IIRin_p0),
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.diff_p1 (IIRin_p1),
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.diff_p2 (IIRin_p2),
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.diff_p3 (IIRin_p3),
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.diff_p4 (IIRin_p4),
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.diff_p5 (IIRin_p5),
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.diff_p6 (IIRin_p6),
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.diff_p7 (IIRin_p7)
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);
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integer i;
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always @(posedge clk or negedge rstn) begin
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if (!rstn) begin
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for (i = 0; i < 17; i = i + 1) begin
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din_p0_r[i] <= 'h0;
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din_p1_r[i] <= 'h0;
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din_p2_r[i] <= 'h0;
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din_p3_r[i] <= 'h0;
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din_p4_r[i] <= 'h0;
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din_p5_r[i] <= 'h0;
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din_p6_r[i] <= 'h0;
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din_p7_r[i] <= 'h0;
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end
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end
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else if (en) begin
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din_p0_r[0] <= din_p0;
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din_p1_r[0] <= din_p1;
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din_p2_r[0] <= din_p2;
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din_p3_r[0] <= din_p3;
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din_p4_r[0] <= din_p4;
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din_p5_r[0] <= din_p5;
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din_p6_r[0] <= din_p6;
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din_p7_r[0] <= din_p7;
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for (i = 0; i < 16; i = i + 1) begin
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din_p0_r[i+1] <= din_p0_r[i];
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din_p1_r[i+1] <= din_p1_r[i];
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din_p2_r[i+1] <= din_p2_r[i];
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din_p3_r[i+1] <= din_p3_r[i];
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din_p4_r[i+1] <= din_p4_r[i];
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din_p5_r[i+1] <= din_p5_r[i];
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din_p6_r[i+1] <= din_p6_r[i];
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din_p7_r[i+1] <= din_p7_r[i];
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end
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end
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end
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/*
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wire signed [15:0] din_p0_r1;
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wire signed [15:0] din_p1_r1;
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wire signed [15:0] din_p2_r1;
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wire signed [15:0] din_p3_r1;
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wire signed [15:0] din_p4_r1;
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wire signed [15:0] din_p5_r1;
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wire signed [15:0] din_p6_r1;
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wire signed [15:0] din_p7_r1;
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wire signed [15:0] din_p0_r2;
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wire signed [15:0] din_p1_r2;
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wire signed [15:0] din_p2_r2;
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wire signed [15:0] din_p3_r2;
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wire signed [15:0] din_p4_r2;
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wire signed [15:0] din_p5_r2;
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wire signed [15:0] din_p6_r2;
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wire signed [15:0] din_p7_r2;
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wire signed [15:0] din_p0_r3;
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wire signed [15:0] din_p1_r3;
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wire signed [15:0] din_p2_r3;
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wire signed [15:0] din_p3_r3;
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wire signed [15:0] din_p4_r3;
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wire signed [15:0] din_p5_r3;
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wire signed [15:0] din_p6_r3;
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wire signed [15:0] din_p7_r3;
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wire signed [15:0] din_p0_r4;
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wire signed [15:0] din_p1_r4;
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wire signed [15:0] din_p2_r4;
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wire signed [15:0] din_p3_r4;
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wire signed [15:0] din_p4_r4;
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wire signed [15:0] din_p5_r4;
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wire signed [15:0] din_p6_r4;
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wire signed [15:0] din_p7_r4;
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wire signed [15:0] din_p0_r5;
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wire signed [15:0] din_p1_r5;
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wire signed [15:0] din_p2_r5;
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wire signed [15:0] din_p3_r5;
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wire signed [15:0] din_p4_r5;
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wire signed [15:0] din_p5_r5;
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wire signed [15:0] din_p6_r5;
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wire signed [15:0] din_p7_r5;
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wire signed [15:0] din_p0_r6;
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wire signed [15:0] din_p1_r6;
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wire signed [15:0] din_p2_r6;
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wire signed [15:0] din_p3_r6;
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wire signed [15:0] din_p4_r6;
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wire signed [15:0] din_p5_r6;
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wire signed [15:0] din_p6_r6;
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wire signed [15:0] din_p7_r6;
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wire signed [15:0] din_p0_r7;
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wire signed [15:0] din_p1_r7;
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wire signed [15:0] din_p2_r7;
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wire signed [15:0] din_p3_r7;
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wire signed [15:0] din_p4_r7;
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wire signed [15:0] din_p5_r7;
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wire signed [15:0] din_p6_r7;
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wire signed [15:0] din_p7_r7;
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sirv_gnrl_dfflr #(16) dff_din_p0_1(en,din_p0, din_p0_r1 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p1_1(en,din_p1, din_p1_r1 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p2_1(en,din_p2, din_p2_r1 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p3_1(en,din_p3, din_p3_r1 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p4_1(en,din_p4, din_p4_r1 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p5_1(en,din_p5, din_p5_r1 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p6_1(en,din_p6, din_p6_r1 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p7_1(en,din_p7, din_p7_r1 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p0_2(en,din_p0_r1, din_p0_r2 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p1_2(en,din_p1_r1, din_p1_r2 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p2_2(en,din_p2_r1, din_p2_r2 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p3_2(en,din_p3_r1, din_p3_r2 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p4_2(en,din_p4_r1, din_p4_r2 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p5_2(en,din_p5_r1, din_p5_r2 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p6_2(en,din_p6_r1, din_p6_r2 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p7_2(en,din_p7_r1, din_p7_r2 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p0_3(en,din_p0_r2, din_p0_r3 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p1_3(en,din_p1_r2, din_p1_r3 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p2_3(en,din_p2_r2, din_p2_r3 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p3_3(en,din_p3_r2, din_p3_r3 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p4_3(en,din_p4_r2, din_p4_r3 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p5_3(en,din_p5_r2, din_p5_r3 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p6_3(en,din_p6_r2, din_p6_r3 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p7_3(en,din_p7_r2, din_p7_r3 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p0_4(en,din_p0_r3, din_p0_r4 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p1_4(en,din_p1_r3, din_p1_r4 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p2_4(en,din_p2_r3, din_p2_r4 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p3_4(en,din_p3_r3, din_p3_r4 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p4_4(en,din_p4_r3, din_p4_r4 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p5_4(en,din_p5_r3, din_p5_r4 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p6_4(en,din_p6_r3, din_p6_r4 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p7_4(en,din_p7_r3, din_p7_r4 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p0_5(en,din_p0_r4, din_p0_r5 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p1_5(en,din_p1_r4, din_p1_r5 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p2_5(en,din_p2_r4, din_p2_r5 ,clk,rstn);
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sirv_gnrl_dfflr #(16) dff_din_p3_5(en,din_p3_r4, din_p3_r5 ,clk,rstn);
|
|
sirv_gnrl_dfflr #(16) dff_din_p4_5(en,din_p4_r4, din_p4_r5 ,clk,rstn);
|
|
sirv_gnrl_dfflr #(16) dff_din_p5_5(en,din_p5_r4, din_p5_r5 ,clk,rstn);
|
|
sirv_gnrl_dfflr #(16) dff_din_p6_5(en,din_p6_r4, din_p6_r5 ,clk,rstn);
|
|
sirv_gnrl_dfflr #(16) dff_din_p7_5(en,din_p7_r4, din_p7_r5 ,clk,rstn);
|
|
sirv_gnrl_dfflr #(16) dff_din_p0_6(en,din_p0_r5, din_p0_r6 ,clk,rstn);
|
|
sirv_gnrl_dfflr #(16) dff_din_p1_6(en,din_p1_r5, din_p1_r6 ,clk,rstn);
|
|
sirv_gnrl_dfflr #(16) dff_din_p2_6(en,din_p2_r5, din_p2_r6 ,clk,rstn);
|
|
sirv_gnrl_dfflr #(16) dff_din_p3_6(en,din_p3_r5, din_p3_r6 ,clk,rstn);
|
|
sirv_gnrl_dfflr #(16) dff_din_p4_6(en,din_p4_r5, din_p4_r6 ,clk,rstn);
|
|
sirv_gnrl_dfflr #(16) dff_din_p5_6(en,din_p5_r5, din_p5_r6 ,clk,rstn);
|
|
sirv_gnrl_dfflr #(16) dff_din_p6_6(en,din_p6_r5, din_p6_r6 ,clk,rstn);
|
|
sirv_gnrl_dfflr #(16) dff_din_p7_6(en,din_p7_r5, din_p7_r6 ,clk,rstn);
|
|
sirv_gnrl_dfflr #(16) dff_din_p0_7(en,din_p0_r6, din_p0_r7 ,clk,rstn);
|
|
sirv_gnrl_dfflr #(16) dff_din_p1_7(en,din_p1_r6, din_p1_r7 ,clk,rstn);
|
|
sirv_gnrl_dfflr #(16) dff_din_p2_7(en,din_p2_r6, din_p2_r7 ,clk,rstn);
|
|
sirv_gnrl_dfflr #(16) dff_din_p3_7(en,din_p3_r6, din_p3_r7 ,clk,rstn);
|
|
sirv_gnrl_dfflr #(16) dff_din_p4_7(en,din_p4_r6, din_p4_r7 ,clk,rstn);
|
|
sirv_gnrl_dfflr #(16) dff_din_p5_7(en,din_p5_r6, din_p5_r7 ,clk,rstn);
|
|
sirv_gnrl_dfflr #(16) dff_din_p6_7(en,din_p6_r6, din_p6_r7 ,clk,rstn);
|
|
sirv_gnrl_dfflr #(16) dff_din_p7_7(en,din_p7_r6, din_p7_r7 ,clk,rstn);
|
|
*/
|
|
|
|
always @(posedge clk or negedge rstn) begin
|
|
if (!rstn) begin
|
|
for (i = 0; i < 2; i = i + 1) begin
|
|
IIRin_p0_r[i] <= 'h0;
|
|
end
|
|
for (i = 0; i < 4; i = i + 1) begin
|
|
IIRin_p1_r[i] <= 'h0;
|
|
end
|
|
for (i = 0; i < 6; i = i + 1) begin
|
|
IIRin_p2_r[i] <= 'h0;
|
|
end
|
|
for (i = 0; i < 8; i = i + 1) begin
|
|
IIRin_p3_r[i] <= 'h0;
|
|
end
|
|
for (i = 0; i <10; i = i + 1) begin
|
|
IIRin_p4_r[i] <= 'h0;
|
|
end
|
|
for (i = 0; i <12; i = i + 1) begin
|
|
IIRin_p5_r[i] <= 'h0;
|
|
end
|
|
for (i = 0; i <14; i = i + 1) begin
|
|
IIRin_p6_r[i] <= 'h0;
|
|
end
|
|
end
|
|
else if (en) begin
|
|
IIRin_p0_r[0] <= IIRin_p0;
|
|
IIRin_p1_r[0] <= IIRin_p1;
|
|
IIRin_p2_r[0] <= IIRin_p2;
|
|
IIRin_p3_r[0] <= IIRin_p3;
|
|
IIRin_p4_r[0] <= IIRin_p4;
|
|
IIRin_p5_r[0] <= IIRin_p5;
|
|
IIRin_p6_r[0] <= IIRin_p6;
|
|
for (i = 0; i < 1; i = i + 1) begin
|
|
IIRin_p0_r[i+1] <= IIRin_p0_r[i];
|
|
end
|
|
for (i = 0; i < 3; i = i + 1) begin
|
|
IIRin_p1_r[i+1] <= IIRin_p1_r[i];
|
|
end
|
|
for (i = 0; i < 5; i = i + 1) begin
|
|
IIRin_p2_r[i+1] <= IIRin_p2_r[i];
|
|
end
|
|
for (i = 0; i < 7; i = i + 1) begin
|
|
IIRin_p3_r[i+1] <= IIRin_p3_r[i];
|
|
end
|
|
for (i = 0; i < 9; i = i + 1) begin
|
|
IIRin_p4_r[i+1] <= IIRin_p4_r[i];
|
|
end
|
|
for (i = 0; i <11; i = i + 1) begin
|
|
IIRin_p5_r[i+1] <= IIRin_p5_r[i];
|
|
end
|
|
for (i = 0; i <13; i = i + 1) begin
|
|
IIRin_p6_r[i+1] <= IIRin_p6_r[i];
|
|
end
|
|
end
|
|
end
|
|
|
|
|
|
|
|
|
|
|
|
IIR_top #(
|
|
.data_out_width (temp_var_width )
|
|
) inst_iir_top_0 (
|
|
.clk (clk ),
|
|
.rstn (rstn ),
|
|
.en (en ),
|
|
.IIRin_p0 (IIRin_p0 ),
|
|
.IIRin_p1 (IIRin_p1 ),
|
|
.IIRin_p2 (IIRin_p2 ),
|
|
.IIRin_p3 (IIRin_p3 ),
|
|
.IIRin_p4 (IIRin_p4 ),
|
|
.IIRin_p5 (IIRin_p5 ),
|
|
.IIRin_p6 (IIRin_p6 ),
|
|
.IIRin_p7 (IIRin_p7 ),
|
|
.IIRin_p0_r2 (IIRin_p0_r[1] ),
|
|
.IIRin_p1_r4 (IIRin_p1_r[3] ),
|
|
.IIRin_p2_r6 (IIRin_p2_r[5] ),
|
|
.IIRin_p3_r8 (IIRin_p3_r[7] ),
|
|
.IIRin_p4_r10 (IIRin_p4_r[9] ),
|
|
.IIRin_p5_r12 (IIRin_p5_r[11] ),
|
|
.IIRin_p6_r14 (IIRin_p6_r[13] ),
|
|
.a_re (a_re0 ),
|
|
.b_re (b_re0 ),
|
|
.ab_re (ab_re0 ),
|
|
.abb_re (abb_re0 ),
|
|
.ab_pow3_re (ab_pow3_re0 ),
|
|
.ab_pow4_re (ab_pow4_re0 ),
|
|
.ab_pow5_re (ab_pow5_re0 ),
|
|
.ab_pow6_re (ab_pow6_re0 ),
|
|
.ab_pow7_re (ab_pow7_re0 ),
|
|
.b_pow8_re (b_pow8_re0 ),
|
|
.IIRout_p0 (IIRout_p0[0] ),
|
|
.IIRout_p1 (IIRout_p1[0] ),
|
|
.IIRout_p2 (IIRout_p2[0] ),
|
|
.IIRout_p3 (IIRout_p3[0] ),
|
|
.IIRout_p4 (IIRout_p4[0] ),
|
|
.IIRout_p5 (IIRout_p5[0] ),
|
|
.IIRout_p6 (IIRout_p6[0] ),
|
|
.IIRout_p7 (IIRout_p7[0] )
|
|
);
|
|
|
|
IIR_top #(
|
|
.data_out_width (temp_var_width )
|
|
) inst_iir_top_1 (
|
|
.clk (clk ),
|
|
.rstn (rstn ),
|
|
.en (en ),
|
|
.IIRin_p0 (IIRin_p0 ),
|
|
.IIRin_p1 (IIRin_p1 ),
|
|
.IIRin_p2 (IIRin_p2 ),
|
|
.IIRin_p3 (IIRin_p3 ),
|
|
.IIRin_p4 (IIRin_p4 ),
|
|
.IIRin_p5 (IIRin_p5 ),
|
|
.IIRin_p6 (IIRin_p6 ),
|
|
.IIRin_p7 (IIRin_p7 ),
|
|
.IIRin_p0_r2 (IIRin_p0_r[1] ),
|
|
.IIRin_p1_r4 (IIRin_p1_r[3] ),
|
|
.IIRin_p2_r6 (IIRin_p2_r[5] ),
|
|
.IIRin_p3_r8 (IIRin_p3_r[7] ),
|
|
.IIRin_p4_r10 (IIRin_p4_r[9] ),
|
|
.IIRin_p5_r12 (IIRin_p5_r[11] ),
|
|
.IIRin_p6_r14 (IIRin_p6_r[13] ),
|
|
.a_re (a_re1 ),
|
|
.b_re (b_re1 ),
|
|
.ab_re (ab_re1 ),
|
|
.abb_re (abb_re1 ),
|
|
.ab_pow3_re (ab_pow3_re1 ),
|
|
.ab_pow4_re (ab_pow4_re1 ),
|
|
.ab_pow5_re (ab_pow5_re1 ),
|
|
.ab_pow6_re (ab_pow6_re1 ),
|
|
.ab_pow7_re (ab_pow7_re1 ),
|
|
.b_pow8_re (b_pow8_re1 ),
|
|
.IIRout_p0 (IIRout_p0[1] ),
|
|
.IIRout_p1 (IIRout_p1[1] ),
|
|
.IIRout_p2 (IIRout_p2[1] ),
|
|
.IIRout_p3 (IIRout_p3[1] ),
|
|
.IIRout_p4 (IIRout_p4[1] ),
|
|
.IIRout_p5 (IIRout_p5[1] ),
|
|
.IIRout_p6 (IIRout_p6[1] ),
|
|
.IIRout_p7 (IIRout_p7[1] )
|
|
);
|
|
|
|
IIR_top #(
|
|
.data_out_width (temp_var_width )
|
|
) inst_iir_top_2 (
|
|
.clk (clk ),
|
|
.rstn (rstn ),
|
|
.en (en ),
|
|
.IIRin_p0 (IIRin_p0 ),
|
|
.IIRin_p1 (IIRin_p1 ),
|
|
.IIRin_p2 (IIRin_p2 ),
|
|
.IIRin_p3 (IIRin_p3 ),
|
|
.IIRin_p4 (IIRin_p4 ),
|
|
.IIRin_p5 (IIRin_p5 ),
|
|
.IIRin_p6 (IIRin_p6 ),
|
|
.IIRin_p7 (IIRin_p7 ),
|
|
.IIRin_p0_r2 (IIRin_p0_r[1] ),
|
|
.IIRin_p1_r4 (IIRin_p1_r[3] ),
|
|
.IIRin_p2_r6 (IIRin_p2_r[5] ),
|
|
.IIRin_p3_r8 (IIRin_p3_r[7] ),
|
|
.IIRin_p4_r10 (IIRin_p4_r[9] ),
|
|
.IIRin_p5_r12 (IIRin_p5_r[11] ),
|
|
.IIRin_p6_r14 (IIRin_p6_r[13] ),
|
|
.a_re (a_re2 ),
|
|
.b_re (b_re2 ),
|
|
.ab_re (ab_re2 ),
|
|
.abb_re (abb_re2 ),
|
|
.ab_pow3_re (ab_pow3_re2 ),
|
|
.ab_pow4_re (ab_pow4_re2 ),
|
|
.ab_pow5_re (ab_pow5_re2 ),
|
|
.ab_pow6_re (ab_pow6_re2 ),
|
|
.ab_pow7_re (ab_pow7_re2 ),
|
|
.b_pow8_re (b_pow8_re2 ),
|
|
.IIRout_p0 (IIRout_p0[2] ),
|
|
.IIRout_p1 (IIRout_p1[2] ),
|
|
.IIRout_p2 (IIRout_p2[2] ),
|
|
.IIRout_p3 (IIRout_p3[2] ),
|
|
.IIRout_p4 (IIRout_p4[2] ),
|
|
.IIRout_p5 (IIRout_p5[2] ),
|
|
.IIRout_p6 (IIRout_p6[2] ),
|
|
.IIRout_p7 (IIRout_p7[2] )
|
|
);
|
|
|
|
IIR_top #(
|
|
.data_out_width (temp_var_width )
|
|
) inst_iir_top_3 (
|
|
.clk (clk ),
|
|
.rstn (rstn ),
|
|
.en (en ),
|
|
.IIRin_p0 (IIRin_p0 ),
|
|
.IIRin_p1 (IIRin_p1 ),
|
|
.IIRin_p2 (IIRin_p2 ),
|
|
.IIRin_p3 (IIRin_p3 ),
|
|
.IIRin_p4 (IIRin_p4 ),
|
|
.IIRin_p5 (IIRin_p5 ),
|
|
.IIRin_p6 (IIRin_p6 ),
|
|
.IIRin_p7 (IIRin_p7 ),
|
|
.IIRin_p0_r2 (IIRin_p0_r[1] ),
|
|
.IIRin_p1_r4 (IIRin_p1_r[3] ),
|
|
.IIRin_p2_r6 (IIRin_p2_r[5] ),
|
|
.IIRin_p3_r8 (IIRin_p3_r[7] ),
|
|
.IIRin_p4_r10 (IIRin_p4_r[9] ),
|
|
.IIRin_p5_r12 (IIRin_p5_r[11] ),
|
|
.IIRin_p6_r14 (IIRin_p6_r[13] ),
|
|
.a_re (a_re3 ),
|
|
.b_re (b_re3 ),
|
|
.ab_re (ab_re3 ),
|
|
.abb_re (abb_re3 ),
|
|
.ab_pow3_re (ab_pow3_re3 ),
|
|
.ab_pow4_re (ab_pow4_re3 ),
|
|
.ab_pow5_re (ab_pow5_re3 ),
|
|
.ab_pow6_re (ab_pow6_re3 ),
|
|
.ab_pow7_re (ab_pow7_re3 ),
|
|
.b_pow8_re (b_pow8_re3 ),
|
|
.IIRout_p0 (IIRout_p0[3] ),
|
|
.IIRout_p1 (IIRout_p1[3] ),
|
|
.IIRout_p2 (IIRout_p2[3] ),
|
|
.IIRout_p3 (IIRout_p3[3] ),
|
|
.IIRout_p4 (IIRout_p4[3] ),
|
|
.IIRout_p5 (IIRout_p5[3] ),
|
|
.IIRout_p6 (IIRout_p6[3] ),
|
|
.IIRout_p7 (IIRout_p7[3] )
|
|
);
|
|
|
|
IIR_top #(
|
|
.data_out_width (temp_var_width )
|
|
) inst_iir_top_4 (
|
|
.clk (clk ),
|
|
.rstn (rstn ),
|
|
.en (en ),
|
|
.IIRin_p0 (IIRin_p0 ),
|
|
.IIRin_p1 (IIRin_p1 ),
|
|
.IIRin_p2 (IIRin_p2 ),
|
|
.IIRin_p3 (IIRin_p3 ),
|
|
.IIRin_p4 (IIRin_p4 ),
|
|
.IIRin_p5 (IIRin_p5 ),
|
|
.IIRin_p6 (IIRin_p6 ),
|
|
.IIRin_p7 (IIRin_p7 ),
|
|
.IIRin_p0_r2 (IIRin_p0_r[1] ),
|
|
.IIRin_p1_r4 (IIRin_p1_r[3] ),
|
|
.IIRin_p2_r6 (IIRin_p2_r[5] ),
|
|
.IIRin_p3_r8 (IIRin_p3_r[7] ),
|
|
.IIRin_p4_r10 (IIRin_p4_r[9] ),
|
|
.IIRin_p5_r12 (IIRin_p5_r[11] ),
|
|
.IIRin_p6_r14 (IIRin_p6_r[13] ),
|
|
.a_re (a_re4 ),
|
|
.b_re (b_re4 ),
|
|
.ab_re (ab_re4 ),
|
|
.abb_re (abb_re4 ),
|
|
.ab_pow3_re (ab_pow3_re4 ),
|
|
.ab_pow4_re (ab_pow4_re4 ),
|
|
.ab_pow5_re (ab_pow5_re4 ),
|
|
.ab_pow6_re (ab_pow6_re4 ),
|
|
.ab_pow7_re (ab_pow7_re4 ),
|
|
.b_pow8_re (b_pow8_re4 ),
|
|
.IIRout_p0 (IIRout_p0[4] ),
|
|
.IIRout_p1 (IIRout_p1[4] ),
|
|
.IIRout_p2 (IIRout_p2[4] ),
|
|
.IIRout_p3 (IIRout_p3[4] ),
|
|
.IIRout_p4 (IIRout_p4[4] ),
|
|
.IIRout_p5 (IIRout_p5[4] ),
|
|
.IIRout_p6 (IIRout_p6[4] ),
|
|
.IIRout_p7 (IIRout_p7[4] )
|
|
);
|
|
|
|
IIR_top #(
|
|
.data_out_width (temp_var_width )
|
|
) inst_iir_top_5 (
|
|
.clk (clk ),
|
|
.rstn (rstn ),
|
|
.en (en ),
|
|
.IIRin_p0 (IIRin_p0 ),
|
|
.IIRin_p1 (IIRin_p1 ),
|
|
.IIRin_p2 (IIRin_p2 ),
|
|
.IIRin_p3 (IIRin_p3 ),
|
|
.IIRin_p4 (IIRin_p4 ),
|
|
.IIRin_p5 (IIRin_p5 ),
|
|
.IIRin_p6 (IIRin_p6 ),
|
|
.IIRin_p7 (IIRin_p7 ),
|
|
.IIRin_p0_r2 (IIRin_p0_r[1] ),
|
|
.IIRin_p1_r4 (IIRin_p1_r[3] ),
|
|
.IIRin_p2_r6 (IIRin_p2_r[5] ),
|
|
.IIRin_p3_r8 (IIRin_p3_r[7] ),
|
|
.IIRin_p4_r10 (IIRin_p4_r[9] ),
|
|
.IIRin_p5_r12 (IIRin_p5_r[11] ),
|
|
.IIRin_p6_r14 (IIRin_p6_r[13] ),
|
|
.a_re (a_re5 ),
|
|
.b_re (b_re5 ),
|
|
.ab_re (ab_re5 ),
|
|
.abb_re (abb_re5 ),
|
|
.ab_pow3_re (ab_pow3_re5 ),
|
|
.ab_pow4_re (ab_pow4_re5 ),
|
|
.ab_pow5_re (ab_pow5_re5 ),
|
|
.ab_pow6_re (ab_pow6_re5 ),
|
|
.ab_pow7_re (ab_pow7_re5 ),
|
|
.b_pow8_re (b_pow8_re5 ),
|
|
.IIRout_p0 (IIRout_p0[5] ),
|
|
.IIRout_p1 (IIRout_p1[5] ),
|
|
.IIRout_p2 (IIRout_p2[5] ),
|
|
.IIRout_p3 (IIRout_p3[5] ),
|
|
.IIRout_p4 (IIRout_p4[5] ),
|
|
.IIRout_p5 (IIRout_p5[5] ),
|
|
.IIRout_p6 (IIRout_p6[5] ),
|
|
.IIRout_p7 (IIRout_p7[5] )
|
|
);
|
|
|
|
assign sum_IIRout_p0 = IIRout_p0[0] + IIRout_p0[1] +IIRout_p0[2] +IIRout_p0[3] +IIRout_p0[4] +IIRout_p0[5];
|
|
assign sum_IIRout_p1 = IIRout_p1[0] + IIRout_p1[1] +IIRout_p1[2] +IIRout_p1[3] +IIRout_p1[4] +IIRout_p1[5];
|
|
assign sum_IIRout_p2 = IIRout_p2[0] + IIRout_p2[1] +IIRout_p2[2] +IIRout_p2[3] +IIRout_p2[4] +IIRout_p2[5];
|
|
assign sum_IIRout_p3 = IIRout_p3[0] + IIRout_p3[1] +IIRout_p3[2] +IIRout_p3[3] +IIRout_p3[4] +IIRout_p3[5];
|
|
assign sum_IIRout_p4 = IIRout_p4[0] + IIRout_p4[1] +IIRout_p4[2] +IIRout_p4[3] +IIRout_p4[4] +IIRout_p4[5];
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assign sum_IIRout_p5 = IIRout_p5[0] + IIRout_p5[1] +IIRout_p5[2] +IIRout_p5[3] +IIRout_p5[4] +IIRout_p5[5];
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assign sum_IIRout_p6 = IIRout_p6[0] + IIRout_p6[1] +IIRout_p6[2] +IIRout_p6[3] +IIRout_p6[4] +IIRout_p6[5];
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assign sum_IIRout_p7 = IIRout_p7[0] + IIRout_p7[1] +IIRout_p7[2] +IIRout_p7[3] +IIRout_p7[4] +IIRout_p7[5];
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/*trunc #(20, 19, 3) round_u0 (clk, rstn, en, sum_IIRout_p0, sum_IIRout_p0_trunc);
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trunc #(20, 19, 3) round_u1 (clk, rstn, en, sum_IIRout_p1, sum_IIRout_p1_trunc);
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trunc #(20, 19, 3) round_u2 (clk, rstn, en, sum_IIRout_p2, sum_IIRout_p2_trunc);
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trunc #(20, 19, 3) round_u3 (clk, rstn, en, sum_IIRout_p3, sum_IIRout_p3_trunc);
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trunc #(20, 19, 3) round_u4 (clk, rstn, en, sum_IIRout_p4, sum_IIRout_p4_trunc);
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trunc #(20, 19, 3) round_u5 (clk, rstn, en, sum_IIRout_p5, sum_IIRout_p5_trunc);
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trunc #(20, 19, 3) round_u6 (clk, rstn, en, sum_IIRout_p6, sum_IIRout_p6_trunc);
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trunc #(20, 19, 3) round_u7 (clk, rstn, en, sum_IIRout_p7, sum_IIRout_p7_trunc);*/
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always @(posedge clk or negedge rstn) begin
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if (!rstn) begin
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for (i = 0; i < 2; i = i + 1) begin
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sum_IIRout_p6_r[i] <= 'h0;
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end
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for (i = 0; i < 4; i = i + 1) begin
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sum_IIRout_p5_r[i] <= 'h0;
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end
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for (i = 0; i < 6; i = i + 1) begin
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sum_IIRout_p4_r[i] <= 'h0;
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end
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for (i = 0; i < 8; i = i + 1) begin
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sum_IIRout_p3_r[i] <= 'h0;
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end
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for (i = 0; i <10; i = i + 1) begin
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sum_IIRout_p2_r[i] <= 'h0;
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end
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for (i = 0; i <12; i = i + 1) begin
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sum_IIRout_p1_r[i] <= 'h0;
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end
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for (i = 0; i <13; i = i + 1) begin
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sum_IIRout_p0_r[i] <= 'h0;
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end
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end
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else if (en) begin
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sum_IIRout_p6_r[0] <= sum_IIRout_p6;
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sum_IIRout_p5_r[0] <= sum_IIRout_p5;
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sum_IIRout_p4_r[0] <= sum_IIRout_p4;
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sum_IIRout_p3_r[0] <= sum_IIRout_p3;
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sum_IIRout_p2_r[0] <= sum_IIRout_p2;
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sum_IIRout_p1_r[0] <= sum_IIRout_p1;
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sum_IIRout_p0_r[0] <= sum_IIRout_p0;
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for (i = 0; i < 1; i = i + 1) begin
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sum_IIRout_p6_r[i+1] <= sum_IIRout_p6_r[i];
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end
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for (i = 0; i < 3; i = i + 1) begin
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sum_IIRout_p5_r[i+1] <= sum_IIRout_p5_r[i];
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end
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for (i = 0; i < 5; i = i + 1) begin
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sum_IIRout_p4_r[i+1] <= sum_IIRout_p4_r[i];
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end
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for (i = 0; i < 7; i = i + 1) begin
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sum_IIRout_p3_r[i+1] <= sum_IIRout_p3_r[i];
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end
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for (i = 0; i < 9; i = i + 1) begin
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sum_IIRout_p2_r[i+1] <= sum_IIRout_p2_r[i];
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end
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for (i = 0; i <11; i = i + 1) begin
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sum_IIRout_p1_r[i+1] <= sum_IIRout_p1_r[i];
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end
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for (i = 0; i <12; i = i + 1) begin
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sum_IIRout_p0_r[i+1] <= sum_IIRout_p0_r[i];
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end
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end
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end
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assign dout_p0_r0 = {{3{din_p0_r[16][15]}},din_p0_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p1_r[11]; // y(8n-119)
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assign dout_p1_r0 = {{3{din_p1_r[16][15]}},din_p1_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p2_r[9]; // y(8n-118)
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assign dout_p2_r0 = {{3{din_p2_r[16][15]}},din_p2_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p3_r[7]; // y(8n-117)
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assign dout_p3_r0 = {{3{din_p3_r[16][15]}},din_p3_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p4_r[5]; // y(8n-116)
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assign dout_p4_r0 = {{3{din_p4_r[16][15]}},din_p4_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p5_r[3]; // y(8n-116)
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assign dout_p5_r0 = {{3{din_p5_r[16][15]}},din_p5_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p6_r[1]; // y(8n-114)
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assign dout_p6_r0 = {{3{din_p6_r[16][15]}},din_p6_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p7; // y(8n-113)
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assign dout_p7_r0 = {{3{din_p7_r[16][15]}},din_p7_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p0_r[12]; // y(8n-112)
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trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u0 (clk, rstn, en, dout_p0_r0, dout_p0);
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trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u1 (clk, rstn, en, dout_p1_r0, dout_p1);
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trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u2 (clk, rstn, en, dout_p2_r0, dout_p2);
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trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u3 (clk, rstn, en, dout_p3_r0, dout_p3);
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trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u4 (clk, rstn, en, dout_p4_r0, dout_p4);
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trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u5 (clk, rstn, en, dout_p5_r0, dout_p5);
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trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u6 (clk, rstn, en, dout_p6_r0, dout_p6);
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trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u7 (clk, rstn, en, dout_p7_r0, dout_p7);
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//
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reg signed [15:0] dout_p0_r2;
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reg signed [15:0] dout_p0_r3;
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reg signed [15:0] dout_p0_r4;
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reg signed [15:0] dout_p0_r5;
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reg signed [15:0] dout_p0_r6;
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always @(posedge clk or negedge rstn)
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if (!rstn)
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begin
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dout_p0_r2 <= 16'd0;
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dout_p0_r3 <= 16'd0;
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dout_p0_r4 <= 16'd0;
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dout_p0_r5 <= 16'd0;
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dout_p0_r6 <= 16'd0;
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end
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else if(en)
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begin
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dout_p0_r2 <= dout_p0;
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dout_p0_r3 <= dout_p0_r2;
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dout_p0_r4 <= dout_p0_r3;
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dout_p0_r5 <= dout_p0_r4;
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dout_p0_r6 <= dout_p0_r5;
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end
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else
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begin
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dout_p0_r2 <= dout_p0_r2;
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dout_p0_r3 <= dout_p0_r3;
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dout_p0_r4 <= dout_p0_r4;
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dout_p0_r5 <= dout_p0_r5;
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dout_p0_r6 <= dout_p0_r6;
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end
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reg [18:0] vldo_diff_r;
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always @(posedge clk or negedge rstn)begin
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if(rstn==1'b0)begin
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|
vldo_diff_r <= 19'b0;
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|
end
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|
else if(en) begin
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|
vldo_diff_r[0] <= vldo_diff;
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|
for(i=0; i<18; i=i+1) begin
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|
vldo_diff_r[i+1] <= vldo_diff_r[i];
|
|
end
|
|
end
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|
else begin
|
|
vldo_diff_r <= vldo_diff_r;
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|
end
|
|
end
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|
wire vldo_r0_h;
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|
wire vldo_r0_l;
|
|
reg vldo_r0;
|
|
always @(posedge clk or negedge rstn)begin
|
|
if(rstn==1'b0)begin
|
|
vldo_r0 <= 0;
|
|
end
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|
else if(vldo_r0_h)begin
|
|
vldo_r0 <= 1;
|
|
end
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|
else if(vldo_r0_l)begin
|
|
vldo_r0 <= 0;
|
|
end
|
|
end
|
|
assign vldo_r0_l = (dout_p0_r0 == 0 && dout_p0 == 0 && dout_p0_r2 == 0 && dout_p0_r3 == 0 && dout_p0_r4 == 0 && dout_p0_r5 == 0&& dout_p0_r6 == 0);
|
|
assign vldo_r0_h = vldo_diff_r[17] == 0 && vldo_diff_r[16] == 1 ;
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|
assign vldo = vldo_r0;
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endmodule
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