DW_mult_pipe.v
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输出8路转4路后和原来的8路进行比较;
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2025-03-11 19:48:56 +08:00 |
clk_gen.v
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增加了八倍内插模块;
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2025-03-11 19:36:24 +08:00 |
tb_DW_iir_dc.v
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IIR滤波器使用IP核;
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2025-03-11 19:40:19 +08:00 |
tb_diff.v
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增加了八倍内插模块;
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2025-03-11 19:36:24 +08:00 |
tb_iir.v
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增加了八倍内插模块;
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2025-03-11 19:36:24 +08:00 |
tb_mean2.v
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增加了八倍内插模块;
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2025-03-11 19:36:24 +08:00 |
tb_mean4.v
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增加了八倍内插模块;
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2025-03-11 19:36:24 +08:00 |
tb_mean4_top.v
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增加了八倍内插模块;
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2025-03-11 19:36:24 +08:00 |
tb_mean8_top.v
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增加了八倍内插模块;
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2025-03-11 19:36:24 +08:00 |
tb_z_dsp.v
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八倍内插模块的使能改为时钟二分频;
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2025-03-11 19:44:53 +08:00 |
tb_z_dsp_en_Test.v
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八倍内插模块的使能改为时钟二分频;
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2025-03-11 19:44:53 +08:00 |