38 lines
845 B
Verilog
38 lines
845 B
Verilog
module FixRound #(
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parameter integer Data_width = 8
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,parameter integer Fix_frac_coef_width = 31//division
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)
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(
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input clk
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,input rstn
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,input en
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,input signed [Data_width-1:0] din
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,output signed [Data_width-1:0] dout
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);
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reg signed [Data_width-1:0] din_round;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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begin
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din_round <= 'h0;
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end
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else if(en) begin
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if(din[Data_width-1] == 1'b0)
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begin
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din_round <= din + {{1'b1},{(Fix_frac_coef_width-1){1'b0}}};
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end
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else if (din[Data_width-1] == 1'b1)
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begin
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din_round <= din + {{1'b1},{(Fix_frac_coef_width-1){1'b0}}} - 1'b1;
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end
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end
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else begin
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din_round <= din_round;
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end
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assign dout = din_round;
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endmodule
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