251 lines
16 KiB
Verilog
251 lines
16 KiB
Verilog
//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : TailCorr_top.v
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// Department :
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// Author : thfu
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.3 2024-05-15 thfu
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module IIR_top #(
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parameter temp_var_width = 20
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,parameter data_out_width = 18
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)
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(
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input rstn
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,input clk
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,input en
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,input signed [15 :0] IIRin_p0 // x(8n+9)
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,input signed [15 :0] IIRin_p1 // x(8n+10)
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,input signed [15 :0] IIRin_p2 // x(8n+11)
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,input signed [15 :0] IIRin_p3 // x(8n+12)
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,input signed [15 :0] IIRin_p4 // x(8n+13)
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,input signed [15 :0] IIRin_p5 // x(8n+14)
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,input signed [15 :0] IIRin_p6 // x(8n+15)
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,input signed [15 :0] IIRin_p7 // x(8n+16)
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,input signed [15 :0] IIRin_p0_r2 // x(8n+9) delay 2M -> x(8n- 7)
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,input signed [15 :0] IIRin_p1_r4 // x(8n+10) delay 4M -> x(8n-22)
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,input signed [15 :0] IIRin_p2_r6 // x(8n+11) delay 6M -> x(8n-37)
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,input signed [15 :0] IIRin_p3_r8 // x(8n+12) delay 8M -> x(8n-52)
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,input signed [15 :0] IIRin_p4_r10 // x(8n+13) delay 10M -> x(8n-67)
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,input signed [15 :0] IIRin_p5_r12 // x(8n+14) delay 12M -> x(8n-82)
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,input signed [15 :0] IIRin_p6_r14 // x(8n+15) delay 14M -> x(8n-97)
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,input signed [31 :0] a_re
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,input signed [31 :0] a_im
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,input signed [31 :0] b_re
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,input signed [31 :0] b_im
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,input signed [31 :0] ab_re
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,input signed [31 :0] ab_im
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,input signed [31 :0] abb_re
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,input signed [31 :0] abb_im
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,input signed [31 :0] ab_pow3_re
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,input signed [31 :0] ab_pow3_im
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,input signed [31 :0] ab_pow4_re
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,input signed [31 :0] ab_pow4_im
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,input signed [31 :0] ab_pow5_re
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,input signed [31 :0] ab_pow5_im
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,input signed [31 :0] ab_pow6_re
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,input signed [31 :0] ab_pow6_im
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,input signed [31 :0] ab_pow7_re
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,input signed [31 :0] ab_pow7_im
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,input signed [31 :0] b_pow8_re
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,input signed [31 :0] b_pow8_im
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,output signed [data_out_width-1 :0] IIRout_p0 // y(8n-8)
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,output signed [data_out_width-1 :0] IIRout_p1 // y(8n-23)
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,output signed [data_out_width-1 :0] IIRout_p2 // y(8n-38)
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,output signed [data_out_width-1 :0] IIRout_p3 // y(8n-53)
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,output signed [data_out_width-1 :0] IIRout_p4 // y(8n-68)
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,output signed [data_out_width-1 :0] IIRout_p5 // y(8n-83)
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,output signed [data_out_width-1 :0] IIRout_p6 // y(8n-98)
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,output signed [data_out_width-1 :0] IIRout_p7 // y(8n-113)
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);
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wire signed [temp_var_width-1:0] IIRout_p0_re;
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wire signed [temp_var_width-1:0] IIRout_p1_re;
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wire signed [temp_var_width-1:0] IIRout_p2_re;
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wire signed [temp_var_width-1:0] IIRout_p3_re;
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wire signed [temp_var_width-1:0] IIRout_p4_re;
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wire signed [temp_var_width-1:0] IIRout_p5_re;
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wire signed [temp_var_width-1:0] IIRout_p6_re;
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wire signed [temp_var_width-1:0] IIRout_p7_re;
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wire signed [temp_var_width-1:0] IIRout_p0_im;
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wire signed [temp_var_width-1:0] IIRout_p1_im;
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wire signed [temp_var_width-1:0] IIRout_p2_im;
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wire signed [temp_var_width-1:0] IIRout_p3_im;
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wire signed [temp_var_width-1:0] IIRout_p4_im;
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wire signed [temp_var_width-1:0] IIRout_p5_im;
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wire signed [temp_var_width-1:0] IIRout_p6_im;
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wire signed [temp_var_width-1:0] IIRout_p7_im;
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IIR_Filter_p8 inst_iir_p0 (
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.dinp0 (IIRin_p7 ), // x(8n+16)
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.dinp1 (IIRin_p6 ), // x(8n+15)
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.dinp2 (IIRin_p5 ), // x(8n+14)
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.dinp3 (IIRin_p4 ), // x(8n+13)
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.dinp4 (IIRin_p3 ), // x(8n+12)
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.dinp5 (IIRin_p2 ), // x(8n+11)
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.dinp6 (IIRin_p1 ), // x(8n+10)
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.dinp7 (IIRin_p0 ), // x(8n+9)
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.a_re (a_re ),
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.a_im (a_im ),
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.ab_re (ab_re ),
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.ab_im (ab_im ),
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.abb_re (abb_re ),
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.abb_im (abb_im ),
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.ab_pow3_re (ab_pow3_re ),
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.ab_pow3_im (ab_pow3_im ),
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.ab_pow4_re (ab_pow4_re ),
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.ab_pow4_im (ab_pow4_im ),
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.ab_pow5_re (ab_pow5_re ),
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.ab_pow5_im (ab_pow5_im ),
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.ab_pow6_re (ab_pow6_re ),
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.ab_pow6_im (ab_pow6_im ),
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.ab_pow7_re (ab_pow7_re ),
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.ab_pow7_im (ab_pow7_im ),
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.b_pow8_re (b_pow8_re ),
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.b_pow8_im (b_pow8_im ),
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.dout_re (IIRout_p0_re ), // Re(y(8n-8))
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.dout_im (IIRout_p0_im ) // Im(y(8n-8))
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);
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IIR_Filter_p1 inst_iir_p1 (
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.din_re (IIRin_p0_r2 ), // x(8n-7)
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.dout_r1_re (IIRout_p0_re ), // Re(y(8n-8))
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.dout_r1_im (IIRout_p0_im ), // Im(y(8n-8))
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.a_re (a_re ),
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.a_im (a_im ),
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.b_re (b_re ),
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.b_im (b_im ),
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.dout_re (IIRout_p1_re ), // Re(y(8n-23))
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.dout_im (IIRout_p1_im ) // Im(y(8n-23))
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);
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IIR_Filter_p1 inst_iir_p2 (
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.din_re (IIRin_p1_r4 ), // x(8n-22)
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.dout_r1_re (IIRout_p1_re ), // Re(y(8n-23))
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.dout_r1_im (IIRout_p1_im ), // Im(y(8n-23))
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.a_re (a_re ),
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.a_im (a_im ),
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.b_re (b_re ),
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.b_im (b_im ),
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.dout_re (IIRout_p2_re ), // Re(y(8n-38))
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.dout_im (IIRout_p2_im ) // Im(y(8n-38))
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);
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IIR_Filter_p1 inst_iir_p3 (
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.din_re (IIRin_p2_r6 ), // x(8n-37)
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.dout_r1_re (IIRout_p2_re ), // Re(y(8n-38))
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.dout_r1_im (IIRout_p2_im ), // Im(y(8n-38))
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.a_re (a_re ),
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.a_im (a_im ),
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.b_re (b_re ),
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.b_im (b_im ),
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.dout_re (IIRout_p3_re ), // Re(y(8n-53))
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.dout_im (IIRout_p3_im ) // Im(y(8n-53))
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);
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IIR_Filter_p1 inst_iir_p4 (
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.din_re (IIRin_p3_r8 ), // x(8n-52)
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.dout_r1_re (IIRout_p3_re ), // Re(y(8n-53))
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.dout_r1_im (IIRout_p3_im ), // Im(y(8n-53))
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.a_re (a_re ),
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.a_im (a_im ),
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.b_re (b_re ),
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.b_im (b_im ),
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.dout_re (IIRout_p4_re ), // Re(y(8n-68))
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.dout_im (IIRout_p4_im ) // Im(y(8n-68))
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);
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IIR_Filter_p1 inst_iir_p5 (
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.din_re (IIRin_p4_r10 ), // x(8n-67)
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.dout_r1_re (IIRout_p4_re ), // Re(y(8n-68))
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.dout_r1_im (IIRout_p4_im ), // Im(y(8n-68))
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.a_re (a_re ),
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.a_im (a_im ),
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.b_re (b_re ),
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.b_im (b_im ),
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.dout_re (IIRout_p5_re ), // Re(y(8n-83))
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.dout_im (IIRout_p5_im ) // Im(y(8n-83))
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);
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IIR_Filter_p1 inst_iir_p6 (
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.din_re (IIRin_p5_r12 ), // x(8n-82)
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.dout_r1_re (IIRout_p5_re ), // Re(y(8n-83))
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.dout_r1_im (IIRout_p5_im ), // Im(y(8n-83))
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.a_re (a_re ),
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.a_im (a_im ),
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.b_re (b_re ),
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.b_im (b_im ),
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.dout_re (IIRout_p6_re ), // Re(y(8n-98))
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.dout_im (IIRout_p6_im ) // Im(y(8n-98))
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);
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IIR_Filter_p1 inst_iir_p7 (
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.din_re (IIRin_p6_r14 ), // x(8n-97)
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.dout_r1_re (IIRout_p6_re ), // Re(y(8n-98))
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.dout_r1_im (IIRout_p6_im ), // Im(y(8n-98))
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.a_re (a_re ),
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.a_im (a_im ),
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.b_re (b_re ),
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.b_im (b_im ),
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.dout_re (IIRout_p7_re ), // Re(y(8n-113))
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.dout_im (IIRout_p7_im ) // Im(y(8n-113))
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);
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assign IIRout_p0 = IIRout_p0_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-8)
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assign IIRout_p1 = IIRout_p1_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-23)
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assign IIRout_p2 = IIRout_p2_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-38)
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assign IIRout_p3 = IIRout_p3_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-53)
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assign IIRout_p4 = IIRout_p4_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-68)
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assign IIRout_p5 = IIRout_p5_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-83)
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assign IIRout_p6 = IIRout_p6_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-98)
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assign IIRout_p7 = IIRout_p7_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-113)
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endmodule
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