142 lines
3.6 KiB
Verilog
142 lines
3.6 KiB
Verilog
|
|
module diff_p
|
|
(
|
|
input rstn
|
|
,input clk
|
|
,input en
|
|
,input vldi
|
|
,input signed [15:0] din0
|
|
,input signed [15:0] din1
|
|
,input signed [15:0] din2
|
|
,input signed [15:0] din3
|
|
,input signed [15:0] din4
|
|
,input signed [15:0] din5
|
|
,input signed [15:0] din6
|
|
,input signed [15:0] din7
|
|
,input signed [15:0] din8
|
|
,input signed [15:0] din9
|
|
,input signed [15:0] dina
|
|
,input signed [15:0] dinb
|
|
,input signed [15:0] dinc
|
|
,input signed [15:0] dind
|
|
,input signed [15:0] dine
|
|
,input signed [15:0] dinf
|
|
,output vldo
|
|
,output signed [15:0] diff_p0
|
|
,output signed [15:0] diff_p1
|
|
,output signed [15:0] diff_p2
|
|
,output signed [15:0] diff_p3
|
|
,output signed [15:0] diff_p4
|
|
,output signed [15:0] diff_p5
|
|
,output signed [15:0] diff_p6
|
|
,output signed [15:0] diff_p7
|
|
,output signed [15:0] diff_p8
|
|
,output signed [15:0] diff_p9
|
|
,output signed [15:0] diff_pa
|
|
,output signed [15:0] diff_pb
|
|
,output signed [15:0] diff_pc
|
|
,output signed [15:0] diff_pd
|
|
,output signed [15:0] diff_pe
|
|
,output signed [15:0] diff_pf
|
|
|
|
);
|
|
reg signed [15:0] dinf_r1;
|
|
|
|
sirv_gnrl_dfflr #(16) din_pf_1(en,dinf, dinf_r1 ,clk,rstn);
|
|
|
|
reg signed [15:0] diff_p0_r1;
|
|
reg signed [15:0] diff_p1_r1;
|
|
reg signed [15:0] diff_p2_r1;
|
|
reg signed [15:0] diff_p3_r1;
|
|
reg signed [15:0] diff_p4_r1;
|
|
reg signed [15:0] diff_p5_r1;
|
|
reg signed [15:0] diff_p6_r1;
|
|
reg signed [15:0] diff_p7_r1;
|
|
reg signed [15:0] diff_p8_r1;
|
|
reg signed [15:0] diff_p9_r1;
|
|
reg signed [15:0] diff_pa_r1;
|
|
reg signed [15:0] diff_pb_r1;
|
|
reg signed [15:0] diff_pc_r1;
|
|
reg signed [15:0] diff_pd_r1;
|
|
reg signed [15:0] diff_pe_r1;
|
|
reg signed [15:0] diff_pf_r1;
|
|
|
|
always @(posedge clk or negedge rstn)begin
|
|
if(rstn==1'b0)begin
|
|
diff_p0_r1 <= 0;
|
|
diff_p1_r1 <= 0;
|
|
diff_p2_r1 <= 0;
|
|
diff_p3_r1 <= 0;
|
|
diff_p4_r1 <= 0;
|
|
diff_p5_r1 <= 0;
|
|
diff_p6_r1 <= 0;
|
|
diff_p7_r1 <= 0;
|
|
diff_p8_r1 <= 0;
|
|
diff_p9_r1 <= 0;
|
|
diff_pa_r1 <= 0;
|
|
diff_pb_r1 <= 0;
|
|
diff_pc_r1 <= 0;
|
|
diff_pd_r1 <= 0;
|
|
diff_pe_r1 <= 0;
|
|
diff_pf_r1 <= 0;
|
|
end
|
|
else if(en)begin
|
|
diff_p0_r1 <= din0 - dinf_r1;
|
|
diff_p1_r1 <= din1 - din0;
|
|
diff_p2_r1 <= din2 - din1;
|
|
diff_p3_r1 <= din3 - din2;
|
|
diff_p4_r1 <= din4 - din3;
|
|
diff_p5_r1 <= din5 - din4;
|
|
diff_p6_r1 <= din6 - din5;
|
|
diff_p7_r1 <= din7 - din6;
|
|
diff_p8_r1 <= din8 - din7;
|
|
diff_p9_r1 <= din9 - din8 ;
|
|
diff_pa_r1 <= dina - din9 ;
|
|
diff_pb_r1 <= dinb - dina;
|
|
diff_pc_r1 <= dinc - dinb;
|
|
diff_pd_r1 <= dind - dinc;
|
|
diff_pe_r1 <= dine - dind;
|
|
diff_pf_r1 <= dinf - dine;
|
|
end
|
|
else begin
|
|
diff_p0_r1 <= diff_p0_r1;
|
|
diff_p1_r1 <= diff_p1_r1;
|
|
diff_p2_r1 <= diff_p2_r1;
|
|
diff_p3_r1 <= diff_p3_r1;
|
|
diff_p4_r1 <= diff_p4_r1;
|
|
diff_p5_r1 <= diff_p5_r1;
|
|
diff_p6_r1 <= diff_p6_r1;
|
|
diff_p7_r1 <= diff_p7_r1;
|
|
diff_p8_r1 <= diff_p8_r1;
|
|
diff_p9_r1 <= diff_p9_r1;
|
|
diff_pa_r1 <= diff_pa_r1;
|
|
diff_pb_r1 <= diff_pb_r1;
|
|
diff_pc_r1 <= diff_pc_r1;
|
|
diff_pd_r1 <= diff_pd_r1;
|
|
diff_pe_r1 <= diff_pe_r1;
|
|
diff_pf_r1 <= diff_pf_r1;
|
|
end
|
|
end
|
|
|
|
assign diff_p0 = diff_p0_r1;
|
|
assign diff_p1 = diff_p1_r1;
|
|
assign diff_p2 = diff_p2_r1;
|
|
assign diff_p3 = diff_p3_r1;
|
|
assign diff_p4 = diff_p4_r1;
|
|
assign diff_p5 = diff_p5_r1;
|
|
assign diff_p6 = diff_p6_r1;
|
|
assign diff_p7 = diff_p7_r1;
|
|
assign diff_p8 = diff_p8_r1;
|
|
assign diff_p9 = diff_p9_r1;
|
|
assign diff_pa = diff_pa_r1;
|
|
assign diff_pb = diff_pb_r1;
|
|
assign diff_pc = diff_pc_r1;
|
|
assign diff_pd = diff_pd_r1;
|
|
assign diff_pe = diff_pe_r1;
|
|
assign diff_pf = diff_pf_r1;
|
|
|
|
sirv_gnrl_dffr #(1) vldo_1(vldi, vldo ,clk,rstn);
|
|
|
|
endmodule
|
|
|