481 lines
20 KiB
Verilog
481 lines
20 KiB
Verilog
module z_dsp
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(
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input rstn
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,input clk
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,input en
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//,input tc_bypass //NC
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,input [ 3:0] vldi_coef
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,input vldi_data
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//,input [1:0] intp_mode //NC
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//,input [1:0] dac_mode_sel //NC
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,input signed [15:0] din0
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,input signed [15:0] din1
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,input signed [15:0] din2
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,input signed [15:0] din3
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,input signed [15:0] din4
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,input signed [15:0] din5
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,input signed [15:0] din6
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,input signed [15:0] din7
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,input signed [15:0] din8
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,input signed [15:0] din9
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,input signed [15:0] dina
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,input signed [15:0] dinb
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,input signed [15:0] dinc
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,input signed [15:0] dind
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,input signed [15:0] dine
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,input signed [15:0] dinf
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,input signed [31:0] a0_re
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,input signed [31:0] b0_re
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,input signed [31:0] a1_re
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,input signed [31:0] b1_re
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,input signed [31:0] a2_re
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,input signed [31:0] b2_re
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,input signed [31:0] a3_re
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,input signed [31:0] b3_re
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// 复数端口
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`ifdef COMPLEX
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input signed [31:0] a0_im;
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input signed [31:0] b0_im;
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input signed [31:0] a1_im;
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input signed [31:0] b1_im;
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input signed [31:0] a2_im;
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input signed [31:0] b2_im;
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input signed [31:0] a3_im;
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input signed [31:0] b3_im;
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`endif
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,output signed [15:0] dout0
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,output signed [15:0] dout1
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,output signed [15:0] dout2
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,output signed [15:0] dout3
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,output signed [15:0] dout4
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,output signed [15:0] dout5
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,output signed [15:0] dout6
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,output signed [15:0] dout7
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,output signed [15:0] dout8
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,output signed [15:0] dout9
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,output signed [15:0] douta
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,output signed [15:0] doutb
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,output signed [15:0] doutc
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,output signed [15:0] doutd
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,output signed [15:0] doute
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,output signed [15:0] doutf
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,output vldo
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);
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wire signed [15:0] IIR_out;
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wire signed [31:0] ao_re [3:0];
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wire signed [31:0] ab_re [3:0];
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wire signed [31:0] abb_re [3:0];
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wire signed [31:0] ab_pow3_re [3:0];
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wire signed [31:0] ab_pow4_re [3:0];
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wire signed [31:0] ab_pow5_re [3:0];
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wire signed [31:0] ab_pow6_re [3:0];
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wire signed [31:0] ab_pow7_re [3:0];
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wire signed [31:0] ab_pow8_re [3:0];
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wire signed [31:0] ab_pow9_re [3:0];
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wire signed [31:0] ab_powa_re [3:0];
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wire signed [31:0] ab_powb_re [3:0];
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wire signed [31:0] ab_powc_re [3:0];
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wire signed [31:0] ab_powd_re [3:0];
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wire signed [31:0] ab_powe_re [3:0];
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wire signed [31:0] ab_powf_re [3:0];
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wire signed [31:0] bo_re [3:0];
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wire signed [31:0] b_pow16_re [3:0];
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// 复数信号
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`ifdef COMPLEX
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wire signed [31:0] ao_im [3:0];
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wire signed [31:0] ab_im [3:0];
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wire signed [31:0] abb_im [3:0];
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wire signed [31:0] ab_pow3_im [3:0];
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wire signed [31:0] ab_pow4_im [3:0];
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wire signed [31:0] ab_pow5_im [3:0];
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wire signed [31:0] ab_pow6_im [3:0];
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wire signed [31:0] ab_pow7_im [3:0];
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wire signed [31:0] ab_pow8_im [3:0];
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wire signed [31:0] ab_pow9_im [3:0];
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wire signed [31:0] ab_powa_im [3:0];
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wire signed [31:0] ab_powb_im [3:0];
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wire signed [31:0] ab_powc_im [3:0];
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wire signed [31:0] ab_powd_im [3:0];
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wire signed [31:0] ab_powe_im [3:0];
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wire signed [31:0] ab_powf_im [3:0];
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wire signed [31:0] bo_im [3:0];
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wire signed [31:0] b_pow16_im [3:0];
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`endif
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CoefGen#(
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.data_in_width ( 32 )
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,.coef_width ( 32 )
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,.frac_data_out_width ( 20 )
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,.frac_coef_width ( 31 )
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) u_CoefGen(
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.rstn ( rstn )
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,.clk ( clk )
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,.vldi ( vldi_coef )
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,.a0_re ( a0_re )
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,.b0_re ( b0_re )
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,.a1_re ( a1_re )
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,.b1_re ( b1_re )
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,.a2_re ( a2_re )
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,.b2_re ( b2_re )
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,.a3_re ( a3_re )
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,.b3_re ( b3_re )
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`ifdef COMPLEX
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,.a0_im ( a0_im )
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,.b0_im ( b0_im )
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,.a1_im ( a1_im )
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,.b1_im ( b1_im )
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,.a2_im ( a2_im )
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,.b2_im ( b2_im )
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,.a3_im ( a3_im )
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,.b3_im ( b3_im )
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`endif
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,.a_re0 ( ao_re[0] )
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,.b_re0 ( bo_re[0] )
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,.ab_re0 ( ab_re[0] )
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,.abb_re0 ( abb_re[0] )
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,.ab_pow3_re0 ( ab_pow3_re[0] )
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,.ab_pow4_re0 ( ab_pow4_re[0] )
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,.ab_pow5_re0 ( ab_pow5_re[0] )
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,.ab_pow6_re0 ( ab_pow6_re[0] )
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,.ab_pow7_re0 ( ab_pow7_re[0] )
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,.ab_pow8_re0 ( ab_pow8_re[0] )
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,.ab_pow9_re0 ( ab_pow9_re[0] )
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,.ab_powa_re0 ( ab_powa_re[0] )
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,.ab_powb_re0 ( ab_powb_re[0] )
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,.ab_powc_re0 ( ab_powc_re[0] )
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,.ab_powd_re0 ( ab_powd_re[0] )
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,.ab_powe_re0 ( ab_powe_re[0] )
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,.ab_powf_re0 ( ab_powf_re[0] )
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,.b_pow16_re0 ( b_pow16_re[0] )
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,.a_re1 ( ao_re[1] )
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,.b_re1 ( bo_re[1] )
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,.ab_re1 ( ab_re[1] )
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,.abb_re1 ( abb_re[1] )
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,.ab_pow3_re1 ( ab_pow3_re[1] )
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,.ab_pow4_re1 ( ab_pow4_re[1] )
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,.ab_pow5_re1 ( ab_pow5_re[1] )
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,.ab_pow6_re1 ( ab_pow6_re[1] )
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,.ab_pow7_re1 ( ab_pow7_re[1] )
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,.ab_pow8_re1 ( ab_pow8_re[1] )
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,.ab_pow9_re1 ( ab_pow9_re[1] )
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,.ab_powa_re1 ( ab_powa_re[1] )
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,.ab_powb_re1 ( ab_powb_re[1] )
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,.ab_powc_re1 ( ab_powc_re[1] )
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,.ab_powd_re1 ( ab_powd_re[1] )
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,.ab_powe_re1 ( ab_powe_re[1] )
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,.ab_powf_re1 ( ab_powf_re[1] )
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,.b_pow16_re1 ( b_pow16_re[1] )
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,.a_re2 ( ao_re[2] )
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,.b_re2 ( bo_re[2] )
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,.ab_re2 ( ab_re[2] )
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,.abb_re2 ( abb_re[2] )
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,.ab_pow3_re2 ( ab_pow3_re[2] )
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,.ab_pow4_re2 ( ab_pow4_re[2] )
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,.ab_pow5_re2 ( ab_pow5_re[2] )
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,.ab_pow6_re2 ( ab_pow6_re[2] )
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,.ab_pow7_re2 ( ab_pow7_re[2] )
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,.ab_pow8_re2 ( ab_pow8_re[2] )
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,.ab_pow9_re2 ( ab_pow9_re[2] )
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,.ab_powa_re2 ( ab_powa_re[2] )
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,.ab_powb_re2 ( ab_powb_re[2] )
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,.ab_powc_re2 ( ab_powc_re[2] )
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,.ab_powd_re2 ( ab_powd_re[2] )
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,.ab_powe_re2 ( ab_powe_re[2] )
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,.ab_powf_re2 ( ab_powf_re[2] )
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,.b_pow16_re2 ( b_pow16_re[2] )
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,.a_re3 ( ao_re[3] )
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,.b_re3 ( bo_re[3] )
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,.ab_re3 ( ab_re[3] )
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,.abb_re3 ( abb_re[3] )
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,.ab_pow3_re3 ( ab_pow3_re[3] )
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,.ab_pow4_re3 ( ab_pow4_re[3] )
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,.ab_pow5_re3 ( ab_pow5_re[3] )
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,.ab_pow6_re3 ( ab_pow6_re[3] )
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,.ab_pow7_re3 ( ab_pow7_re[3] )
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,.ab_pow8_re3 ( ab_pow8_re[3] )
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,.ab_pow9_re3 ( ab_pow9_re[3] )
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,.ab_powa_re3 ( ab_powa_re[3] )
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,.ab_powb_re3 ( ab_powb_re[3] )
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,.ab_powc_re3 ( ab_powc_re[3] )
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,.ab_powd_re3 ( ab_powd_re[3] )
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,.ab_powe_re3 ( ab_powe_re[3] )
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,.ab_powf_re3 ( ab_powf_re[3] )
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,.b_pow16_re3 ( b_pow16_re[3] )
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`ifdef COMPLEX
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,.a_im0 ( ao_im[0] )
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,.b_im0 ( bo_im[0] )
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,.ab_im0 ( ab_im[0] )
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,.abb_im0 ( abb_im[0] )
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,.ab_pow3_im0 ( ab_pow3_im[0] )
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,.ab_pow4_im0 ( ab_pow4_im[0] )
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,.ab_pow5_im0 ( ab_pow5_im[0] )
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,.ab_pow6_im0 ( ab_pow6_im[0] )
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,.ab_pow7_im0 ( ab_pow7_im[0] )
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,.ab_pow8_im0 ( ab_pow8_im[0] )
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,.ab_pow9_im0 ( ab_pow9_im[0] )
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,.ab_powa_im0 ( ab_powa_im[0] )
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,.ab_powb_im0 ( ab_powb_im[0] )
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,.ab_powc_im0 ( ab_powc_im[0] )
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,.ab_powd_im0 ( ab_powd_im[0] )
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,.ab_powe_im0 ( ab_powe_im[0] )
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,.ab_powf_im0 ( ab_powf_im[0] )
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,.b_pow16_im0 ( b_pow16_im[0] )
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,.a_im1 ( ao_im[1] )
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,.b_im1 ( bo_im[1] )
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,.ab_im1 ( ab_im[1] )
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,.abb_im1 ( abb_im[1] )
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,.ab_pow3_im1 ( ab_pow3_im[1] )
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,.ab_pow4_im1 ( ab_pow4_im[1] )
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,.ab_pow5_im1 ( ab_pow5_im[1] )
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,.ab_pow6_im1 ( ab_pow6_im[1] )
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,.ab_pow7_im1 ( ab_pow7_im[1] )
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,.ab_pow8_im1 ( ab_pow8_im[1] )
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,.ab_pow9_im1 ( ab_pow9_im[1] )
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,.ab_powa_im1 ( ab_powa_im[1] )
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,.ab_powb_im1 ( ab_powb_im[1] )
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,.ab_powc_im1 ( ab_powc_im[1] )
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,.ab_powd_im1 ( ab_powd_im[1] )
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,.ab_powe_im1 ( ab_powe_im[1] )
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,.ab_powf_im1 ( ab_powf_im[1] )
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,.b_pow16_im1 ( b_pow16_im[1] )
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,.a_im2 ( ao_im[2] )
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,.b_im2 ( bo_im[2] )
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,.ab_im2 ( ab_im[2] )
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,.abb_im2 ( abb_im[2] )
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,.ab_pow3_im2 ( ab_pow3_im[2] )
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,.ab_pow4_im2 ( ab_pow4_im[2] )
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,.ab_pow5_im2 ( ab_pow5_im[2] )
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,.ab_pow6_im2 ( ab_pow6_im[2] )
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,.ab_pow7_im2 ( ab_pow7_im[2] )
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,.ab_pow8_im2 ( ab_pow8_im[2] )
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,.ab_pow9_im2 ( ab_pow9_im[2] )
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,.ab_powa_im2 ( ab_powa_im[2] )
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,.ab_powb_im2 ( ab_powb_im[2] )
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,.ab_powc_im2 ( ab_powc_im[2] )
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,.ab_powd_im2 ( ab_powd_im[2] )
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,.ab_powe_im2 ( ab_powe_im[2] )
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,.ab_powf_im2 ( ab_powf_im[2] )
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,.b_pow16_im2 ( b_pow16_im[2] )
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,.a_im3 ( ao_im[3] )
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,.b_im3 ( bo_im[3] )
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,.ab_im3 ( ab_im[3] )
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,.abb_im3 ( abb_im[3] )
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,.ab_pow3_im3 ( ab_pow3_im[3] )
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,.ab_pow4_im3 ( ab_pow4_im[3] )
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,.ab_pow5_im3 ( ab_pow5_im[3] )
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,.ab_pow6_im3 ( ab_pow6_im[3] )
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,.ab_pow7_im3 ( ab_pow7_im[3] )
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,.ab_pow8_im3 ( ab_pow8_im[3] )
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,.ab_pow9_im3 ( ab_pow9_im[3] )
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,.ab_powa_im3 ( ab_powa_im[3] )
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,.ab_powb_im3 ( ab_powb_im[3] )
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,.ab_powc_im3 ( ab_powc_im[3] )
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,.ab_powd_im3 ( ab_powd_im[3] )
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,.ab_powe_im3 ( ab_powe_im[3] )
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,.ab_powf_im3 ( ab_powf_im[3] )
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,.b_pow16_im3 ( b_pow16_im[3] )
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`endif
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);
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wire signed [15:0] dout_0;
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wire signed [15:0] dout_1;
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wire signed [15:0] dout_2;
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wire signed [15:0] dout_3;
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wire signed [15:0] dout_4;
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wire signed [15:0] dout_5;
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wire signed [15:0] dout_6;
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wire signed [15:0] dout_7;
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wire vldo_TC;
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TailCorr_top u_TailCorr_top(
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.rstn ( rstn )
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,.clk ( clk )
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,.en ( en )
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,.vldi ( vldi_data )
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,.din0 ( din0 )
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,.din1 ( din1 )
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,.din2 ( din2 )
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,.din3 ( din3 )
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,.din4 ( din4 )
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,.din5 ( din5 )
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,.din6 ( din6 )
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,.din7 ( din7 )
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,.din8 ( din8 )
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,.din9 ( din9 )
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,.dina ( dina )
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,.dinb ( dinb )
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,.dinc ( dinc )
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,.dind ( dind )
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,.dine ( dine )
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,.dinf ( dinf )
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,.a_re0 ( ao_re[0] )
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,.b_re0 ( bo_re[0] )
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,.ab_re0 ( ab_re[0] )
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,.abb_re0 ( abb_re[0] )
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,.ab_pow3_re0 ( ab_pow3_re[0] )
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,.ab_pow4_re0 ( ab_pow4_re[0] )
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,.ab_pow5_re0 ( ab_pow5_re[0] )
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,.ab_pow6_re0 ( ab_pow6_re[0] )
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,.ab_pow7_re0 ( ab_pow7_re[0] )
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,.ab_pow8_re0 ( ab_pow8_re[0] )
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,.ab_pow9_re0 ( ab_pow9_re[0] )
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,.ab_powa_re0 ( ab_powa_re[0] )
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,.ab_powb_re0 ( ab_powb_re[0] )
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,.ab_powc_re0 ( ab_powc_re[0] )
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,.ab_powd_re0 ( ab_powd_re[0] )
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,.ab_powe_re0 ( ab_powe_re[0] )
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,.ab_powf_re0 ( ab_powf_re[0] )
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,.b_pow16_re0 ( b_pow16_re[0] )
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,.a_re1 ( ao_re[1] )
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,.b_re1 ( bo_re[1] )
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,.ab_re1 ( ab_re[1] )
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,.abb_re1 ( abb_re[1] )
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,.ab_pow3_re1 ( ab_pow3_re[1] )
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,.ab_pow4_re1 ( ab_pow4_re[1] )
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,.ab_pow5_re1 ( ab_pow5_re[1] )
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,.ab_pow6_re1 ( ab_pow6_re[1] )
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,.ab_pow7_re1 ( ab_pow7_re[1] )
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,.ab_pow8_re1 ( ab_pow8_re[1] )
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,.ab_pow9_re1 ( ab_pow9_re[1] )
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,.ab_powa_re1 ( ab_powa_re[1] )
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,.ab_powb_re1 ( ab_powb_re[1] )
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,.ab_powc_re1 ( ab_powc_re[1] )
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,.ab_powd_re1 ( ab_powd_re[1] )
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,.ab_powe_re1 ( ab_powe_re[1] )
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,.ab_powf_re1 ( ab_powf_re[1] )
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,.b_pow16_re1 ( b_pow16_re[1] )
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,.a_re2 ( ao_re[2] )
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,.b_re2 ( bo_re[2] )
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,.ab_re2 ( ab_re[2] )
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,.abb_re2 ( abb_re[2] )
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,.ab_pow3_re2 ( ab_pow3_re[2] )
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,.ab_pow4_re2 ( ab_pow4_re[2] )
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,.ab_pow5_re2 ( ab_pow5_re[2] )
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,.ab_pow6_re2 ( ab_pow6_re[2] )
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,.ab_pow7_re2 ( ab_pow7_re[2] )
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,.ab_pow8_re2 ( ab_pow8_re[2] )
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,.ab_pow9_re2 ( ab_pow9_re[2] )
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,.ab_powa_re2 ( ab_powa_re[2] )
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,.ab_powb_re2 ( ab_powb_re[2] )
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,.ab_powc_re2 ( ab_powc_re[2] )
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,.ab_powd_re2 ( ab_powd_re[2] )
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,.ab_powe_re2 ( ab_powe_re[2] )
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,.ab_powf_re2 ( ab_powf_re[2] )
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,.b_pow16_re2 ( b_pow16_re[2] )
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,.a_re3 ( ao_re[3] )
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,.b_re3 ( bo_re[3] )
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,.ab_re3 ( ab_re[3] )
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,.abb_re3 ( abb_re[3] )
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,.ab_pow3_re3 ( ab_pow3_re[3] )
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,.ab_pow4_re3 ( ab_pow4_re[3] )
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,.ab_pow5_re3 ( ab_pow5_re[3] )
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,.ab_pow6_re3 ( ab_pow6_re[3] )
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,.ab_pow7_re3 ( ab_pow7_re[3] )
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,.ab_pow8_re3 ( ab_pow8_re[3] )
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,.ab_pow9_re3 ( ab_pow9_re[3] )
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,.ab_powa_re3 ( ab_powa_re[3] )
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,.ab_powb_re3 ( ab_powb_re[3] )
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,.ab_powc_re3 ( ab_powc_re[3] )
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,.ab_powd_re3 ( ab_powd_re[3] )
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,.ab_powe_re3 ( ab_powe_re[3] )
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,.ab_powf_re3 ( ab_powf_re[3] )
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,.b_pow16_re3 ( b_pow16_re[3] )
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`ifdef COMPLEX
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,.a_im0 ( ao_im[0] )
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,.b_im0 ( bo_im[0] )
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,.ab_im0 ( ab_im[0] )
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,.abb_im0 ( abb_im[0] )
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,.ab_pow3_im0 ( ab_pow3_im[0] )
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,.ab_pow4_im0 ( ab_pow4_im[0] )
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,.ab_pow5_im0 ( ab_pow5_im[0] )
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,.ab_pow6_im0 ( ab_pow6_im[0] )
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,.ab_pow7_im0 ( ab_pow7_im[0] )
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,.ab_pow8_im0 ( ab_pow8_im[0] )
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,.ab_pow9_im0 ( ab_pow9_im[0] )
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,.ab_powa_im0 ( ab_powa_im[0] )
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,.ab_powb_im0 ( ab_powb_im[0] )
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,.ab_powc_im0 ( ab_powc_im[0] )
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,.ab_powd_im0 ( ab_powd_im[0] )
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,.ab_powe_im0 ( ab_powe_im[0] )
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,.ab_powf_im0 ( ab_powf_im[0] )
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,.b_pow16_im0 ( b_pow16_im[0] )
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,.a_im1 ( ao_im[1] )
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,.b_im1 ( bo_im[1] )
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|
,.ab_im1 ( ab_im[1] )
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,.abb_im1 ( abb_im[1] )
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,.ab_pow3_im1 ( ab_pow3_im[1] )
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,.ab_pow4_im1 ( ab_pow4_im[1] )
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,.ab_pow5_im1 ( ab_pow5_im[1] )
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,.ab_pow6_im1 ( ab_pow6_im[1] )
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,.ab_pow7_im1 ( ab_pow7_im[1] )
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,.ab_pow8_im1 ( ab_pow8_im[1] )
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|
,.ab_pow9_im1 ( ab_pow9_im[1] )
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,.ab_powa_im1 ( ab_powa_im[1] )
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,.ab_powb_im1 ( ab_powb_im[1] )
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,.ab_powc_im1 ( ab_powc_im[1] )
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|
,.ab_powd_im1 ( ab_powd_im[1] )
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,.ab_powe_im1 ( ab_powe_im[1] )
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,.ab_powf_im1 ( ab_powf_im[1] )
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|
,.b_pow16_im1 ( b_pow16_im[1] )
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|
,.a_im2 ( ao_im[2] )
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|
,.b_im2 ( bo_im[2] )
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|
,.ab_im2 ( ab_im[2] )
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|
,.abb_im2 ( abb_im[2] )
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|
,.ab_pow3_im2 ( ab_pow3_im[2] )
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|
,.ab_pow4_im2 ( ab_pow4_im[2] )
|
|
,.ab_pow5_im2 ( ab_pow5_im[2] )
|
|
,.ab_pow6_im2 ( ab_pow6_im[2] )
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|
,.ab_pow7_im2 ( ab_pow7_im[2] )
|
|
,.ab_pow8_im2 ( ab_pow8_im[2] )
|
|
,.ab_pow9_im2 ( ab_pow9_im[2] )
|
|
,.ab_powa_im2 ( ab_powa_im[2] )
|
|
,.ab_powb_im2 ( ab_powb_im[2] )
|
|
,.ab_powc_im2 ( ab_powc_im[2] )
|
|
,.ab_powd_im2 ( ab_powd_im[2] )
|
|
,.ab_powe_im2 ( ab_powe_im[2] )
|
|
,.ab_powf_im2 ( ab_powf_im[2] )
|
|
,.b_pow16_im2 ( b_pow16_im[2] )
|
|
,.a_im3 ( ao_im[3] )
|
|
,.b_im3 ( bo_im[3] )
|
|
,.ab_im3 ( ab_im[3] )
|
|
,.abb_im3 ( abb_im[3] )
|
|
,.ab_pow3_im3 ( ab_pow3_im[3] )
|
|
,.ab_pow4_im3 ( ab_pow4_im[3] )
|
|
,.ab_pow5_im3 ( ab_pow5_im[3] )
|
|
,.ab_pow6_im3 ( ab_pow6_im[3] )
|
|
,.ab_pow7_im3 ( ab_pow7_im[3] )
|
|
,.ab_pow8_im3 ( ab_pow8_im[3] )
|
|
,.ab_pow9_im3 ( ab_pow9_im[3] )
|
|
,.ab_powa_im3 ( ab_powa_im[3] )
|
|
,.ab_powb_im3 ( ab_powb_im[3] )
|
|
,.ab_powc_im3 ( ab_powc_im[3] )
|
|
,.ab_powd_im3 ( ab_powd_im[3] )
|
|
,.ab_powe_im3 ( ab_powe_im[3] )
|
|
,.ab_powf_im3 ( ab_powf_im[3] )
|
|
,.b_pow16_im3 ( b_pow16_im[3] )
|
|
`endif
|
|
,.dout_p0 ( dout0 )
|
|
,.dout_p1 ( dout1 )
|
|
,.dout_p2 ( dout2 )
|
|
,.dout_p3 ( dout3 )
|
|
,.dout_p4 ( dout4 )
|
|
,.dout_p5 ( dout5 )
|
|
,.dout_p6 ( dout6 )
|
|
,.dout_p7 ( dout7 )
|
|
,.dout_p8 ( dout8 )
|
|
,.dout_p9 ( dout9 )
|
|
,.dout_pa ( douta )
|
|
,.dout_pb ( doutb )
|
|
,.dout_pc ( doutc )
|
|
,.dout_pd ( doutd )
|
|
,.dout_pe ( doute )
|
|
,.dout_pf ( doutf )
|
|
,.vldo ( vldo_TC )
|
|
);
|
|
|
|
assign vldo = vldo_TC;
|
|
endmodule
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