85 lines
3.1 KiB
Verilog
85 lines
3.1 KiB
Verilog
//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : Z_dsp.v
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// Department :
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// Author : thfu
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.3 2024-11-09 thfu to fit the addition of IP core
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module z_dsp_wrapper
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(
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input clk,
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input rstn,
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input [1:0] dac_mode_sel, //2'b00:NRZ mode;2'b01:Double data mode;
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//2'b10:Double Double data mode;2'b11:reserve;
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input tc_bypass,
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input [1:0] intp_mode, //2'b00:x1;2'b01:x2,'b10:x4;other:reserve;
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input signed [15:0] din_re,
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input signed [15:0] din_im,
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input signed [31:0] a0_re, //a0's real part
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input signed [31:0] a0_im, //a0's image part
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input signed [31:0] b0_re,
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input signed [31:0] b0_im,
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input signed [31:0] a1_re,
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input signed [31:0] a1_im,
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input signed [31:0] b1_re,
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input signed [31:0] b1_im,
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input signed [31:0] a2_re,
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input signed [31:0] a2_im,
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input signed [31:0] b2_re,
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input signed [31:0] b2_im,
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input signed [31:0] a3_re,
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input signed [31:0] a3_im,
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input signed [31:0] b3_re,
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input signed [31:0] b3_im,
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input signed [31:0] a4_re,
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input signed [31:0] a4_im,
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input signed [31:0] b4_re,
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input signed [31:0] b4_im,
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input signed [31:0] a5_re,
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input signed [31:0] a5_im,
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input signed [31:0] b5_re,
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input signed [31:0] b5_im,
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output signed [15:0] dout0,
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output signed [15:0] dout1,
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output signed [15:0] dout2,
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output signed [15:0] dout3,
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output signed [15:0] dout4,
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output signed [15:0] dout5,
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output signed [15:0] dout6,
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output signed [15:0] dout7,
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output vldo,
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output saturation_0,
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output saturation_1,
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output saturation_2,
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output saturation_3,
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output saturation_4,
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output saturation_5
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);
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endmodule |